📄 at91sam7s64.inc
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.equ AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, (0x0 << 5) /* (AIC) Internal Sources Code Label Level Sensitive */
.equ AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, (0x1 << 5) /* (AIC) Internal Sources Code Label Edge triggered */
.equ AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL, (0x2 << 5) /* (AIC) External Sources Code Label High-level Sensitive */
.equ AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE, (0x3 << 5) /* (AIC) External Sources Code Label Positive Edge triggered */
## -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
.equ AT91C_AIC_NFIQ, (0x1 << 0) /* (AIC) NFIQ Status */
.equ AT91C_AIC_NIRQ, (0x1 << 1) /* (AIC) NIRQ Status */
## -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
.equ AT91C_AIC_DCR_PROT, (0x1 << 0) /* (AIC) Protection Mode */
.equ AT91C_AIC_DCR_GMSK, (0x1 << 1) /* (AIC) General Mask */
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Debug Unit
# *****************************************************************************
# *** Register offset in AT91S_DBGU structure ***
.equ DBGU_CR, ( 0) /* Control Register */
.equ DBGU_MR, ( 4) /* Mode Register */
.equ DBGU_IER, ( 8) /* Interrupt Enable Register */
.equ DBGU_IDR, (12) /* Interrupt Disable Register */
.equ DBGU_IMR, (16) /* Interrupt Mask Register */
.equ DBGU_CSR, (20) /* Channel Status Register */
.equ DBGU_RHR, (24) /* Receiver Holding Register */
.equ DBGU_THR, (28) /* Transmitter Holding Register */
.equ DBGU_BRGR, (32) /* Baud Rate Generator Register */
.equ DBGU_C1R, (64) /* Chip ID1 Register */
.equ DBGU_C2R, (68) /* Chip ID2 Register */
.equ DBGU_FNTR, (72) /* Force NTRST Register */
.equ DBGU_RPR, (256) /* Receive Pointer Register */
.equ DBGU_RCR, (260) /* Receive Counter Register */
.equ DBGU_TPR, (264) /* Transmit Pointer Register */
.equ DBGU_TCR, (268) /* Transmit Counter Register */
.equ DBGU_RNPR, (272) /* Receive Next Pointer Register */
.equ DBGU_RNCR, (276) /* Receive Next Counter Register */
.equ DBGU_TNPR, (280) /* Transmit Next Pointer Register */
.equ DBGU_TNCR, (284) /* Transmit Next Counter Register */
.equ DBGU_PTCR, (288) /* PDC Transfer Control Register */
.equ DBGU_PTSR, (292) /* PDC Transfer Status Register */
## -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
.equ AT91C_US_RSTRX, (0x1 << 2) /* (DBGU) Reset Receiver */
.equ AT91C_US_RSTTX, (0x1 << 3) /* (DBGU) Reset Transmitter */
.equ AT91C_US_RXEN, (0x1 << 4) /* (DBGU) Receiver Enable */
.equ AT91C_US_RXDIS, (0x1 << 5) /* (DBGU) Receiver Disable */
.equ AT91C_US_TXEN, (0x1 << 6) /* (DBGU) Transmitter Enable */
.equ AT91C_US_TXDIS, (0x1 << 7) /* (DBGU) Transmitter Disable */
# -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
.equ AT91C_US_PAR , (0x7 << 9) /* (DBGU) Parity type */
.equ AT91C_US_PAR_EVEN , (0x0 << 9) /* (DBGU) Even Parity */
.equ AT91C_US_PAR_ODD , (0x1 << 9) /* (DBGU) Odd Parity */
.equ AT91C_US_PAR_SPACE , (0x2 << 9) /* (DBGU) Parity forced to 0 (Space) */
.equ AT91C_US_PAR_MARK , (0x3 << 9) /* (DBGU) Parity forced to 1 (Mark) */
.equ AT91C_US_PAR_NONE , (0x4 << 9) /* (DBGU) No Parity */
.equ AT91C_US_PAR_MULTI_DROP , (0x6 << 9) /* (DBGU) Multi-drop mode */
.equ AT91C_US_CHMODE ,(0x3 << 14) /* (DBGU) Channel Mode */
.equ AT91C_US_CHMODE_NORMAL , (0x0 << 14) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
.equ AT91C_US_CHMODE_AUTO , (0x1 << 14) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
.equ AT91C_US_CHMODE_LOCAL , (0x2 << 14) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
.equ AT91C_US_CHMODE_REMOTE , (0x3 << 14) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
# -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
.equ AT91C_US_RXRDY , (0x1 << 0) /* (DBGU) RXRDY Interrupt */
.equ AT91C_US_TXRDY , (0x1 << 1) /* (DBGU) TXRDY Interrupt */
.equ AT91C_US_ENDRX , (0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
.equ AT91C_US_ENDTX , (0x1 << 4) /* (DBGU) End of Transmit Interrupt */
.equ AT91C_US_OVRE , (0x1 << 5) /* (DBGU) Overrun Interrupt */
.equ AT91C_US_FRAME , (0x1 << 6) /* (DBGU) Framing Error Interrupt */
.equ AT91C_US_PARE , (0x1 << 7) /* (DBGU) Parity Error Interrupt */
.equ AT91C_US_TXEMPTY , (0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
.equ AT91C_US_TXBUFE , (0x1 << 11) /* (DBGU) TXBUFE Interrupt */
.equ AT91C_US_RXBUFF , (0x1 << 12) /* (DBGU) RXBUFF Interrupt */
.equ AT91C_US_COMM_TX , (0x1 << 30) /* (DBGU) COMM_TX Interrupt */
.equ AT91C_US_COMM_RX , (0x1 << 31) /* (DBGU) COMM_RX Interrupt */
# -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
# -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
# -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
# -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
.equ AT91C_US_FORCE_NTRST , (0x1 << 0) /* (DBGU) Force NTRST in JTAG */
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Peripheral Data Controller
# *****************************************************************************
# *** Register offset in AT91S_PDC structure ***
.equ PDC_RPR , ( 0) /* Receive Pointer Register */
.equ PDC_RCR , ( 4) /* Receive Counter Register */
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