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.equ SYSC_PIOA_IFDR, (1060) /* Input Filter Disable Register */
.equ SYSC_PIOA_IFSR, (1064) /* Input Filter Status Register */
.equ SYSC_PIOA_SODR, (1072) /* Set Output Data Register */
.equ SYSC_PIOA_CODR, (1076) /* Clear Output Data Register */
.equ SYSC_PIOA_ODSR, (1080) /* Output Data Status Register */
.equ SYSC_PIOA_PDSR, (1084) /* Pin Data Status Register */
.equ SYSC_PIOA_IER, (1088) /* Interrupt Enable Register */
.equ SYSC_PIOA_IDR, (1092) /* Interrupt Disable Register */
.equ SYSC_PIOA_IMR, (1096) /* Interrupt Mask Register */
.equ SYSC_PIOA_ISR, (1100) /* Interrupt Status Register */
.equ SYSC_PIOA_MDER, (1104) /* Multi-driver Enable Register */
.equ SYSC_PIOA_MDDR, (1108) /* Multi-driver Disable Register */
.equ SYSC_PIOA_MDSR, (1112) /* Multi-driver Status Register */
.equ SYSC_PIOA_PPUDR, (1120) /* Pull-up Disable Register */
.equ SYSC_PIOA_PPUER, (1124) /* Pull-up Enable Register */
.equ SYSC_PIOA_PPUSR, (1128) /* Pad Pull-up Status Register */
.equ SYSC_PIOA_ASR, (1136) /* Select A Register */
.equ SYSC_PIOA_BSR, (1140) /* Select B Register */
.equ SYSC_PIOA_ABSR, (1144) /* AB Select Status Register */
.equ SYSC_PIOA_OWER, (1184) /* Output Write Enable Register */
.equ SYSC_PIOA_OWDR, (1188) /* Output Write Disable Register */
.equ SYSC_PIOA_OWSR, (1192) /* Output Write Status Register */
.equ SYSC_PMC_SCER, (3072) /* System Clock Enable Register */
.equ SYSC_PMC_SCDR, (3076) /* System Clock Disable Register */
.equ SYSC_PMC_SCSR, (3080) /* System Clock Status Register */
.equ SYSC_PMC_PCER, (3088) /* Peripheral Clock Enable Register */
.equ SYSC_PMC_PCDR, (3092) /* Peripheral Clock Disable Register */
.equ SYSC_PMC_PCSR, (3096) /* Peripheral Clock Status Register */
.equ SYSC_PMC_MOR, (3104) /* Main Oscillator Register */
.equ SYSC_PMC_MCFR, (3108) /* Main Clock Frequency Register */
.equ SYSC_PMC_PLLR, (3116) /* PLL Register */
.equ SYSC_PMC_MCKR, (3120) /* Master Clock Register */
.equ SYSC_PMC_PCKR, (3136) /* Programmable Clock Register */
.equ SYSC_PMC_IER, (3168) /* Interrupt Enable Register */
.equ SYSC_PMC_IDR, (3172) /* Interrupt Disable Register */
.equ SYSC_PMC_SR, (3176) /* Status Register */
.equ SYSC_PMC_IMR, (3180) /* Interrupt Mask Register */
.equ SYSC_RSTC_RCR, (3328) /* Reset Control Register */
.equ SYSC_RSTC_RSR, (3332) /* Reset Status Register */
.equ SYSC_RSTC_RMR, (3336) /* Reset Mode Register */
.equ SYSC_RTTC_RTMR, (3360) /* Real-time Mode Register */
.equ SYSC_RTTC_RTAR, (3364) /* Real-time Alarm Register */
.equ SYSC_RTTC_RTVR, (3368) /* Real-time Value Register */
.equ SYSC_RTTC_RTSR, (3372) /* Real-time Status Register */
.equ SYSC_PITC_PIMR, (3376) /* Period Interval Mode Register */
.equ SYSC_PITC_PISR, (3380) /* Period Interval Status Register */
.equ SYSC_PITC_PIVR, (3384) /* Period Interval Value Register */
.equ SYSC_PITC_PIIR, (3388) /* Period Interval Image Register */
.equ SYSC_WDTC_WDCR, (3392) /* Watchdog Control Register */
.equ SYSC_WDTC_WDMR, (3396) /* Watchdog Mode Register */
.equ SYSC_WDTC_WDSR, (3400) /* Watchdog Status Register */
.equ SYSC_SYSC_VRPM, (3424) /* Voltage Regulator Power Mode Register
/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */
.equ AT91C_SYSC_PSTDBY, (0x1 << 0) /* (SYSC) Voltage Regulator Power Mode*/
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
# *****************************************************************************
# *** Register offset in AT91S_AIC structure ***
.equ AIC_SMR, ( 0) /* Source Mode Register */
.equ AIC_SVR, (128) /* Source Vector Register */
.equ AIC_IVR, (256) /* IRQ Vector Register */
.equ AIC_FVR, (260) /* FIQ Vector Register */
.equ AIC_ISR, (264) /* Interrupt Status Register */
.equ AIC_IPR, (268) /* Interrupt Pending Register */
.equ AIC_IMR, (272) /* Interrupt Mask Register */
.equ AIC_CISR, (276) /* Core Interrupt Status Register */
.equ AIC_IECR, (288) /* Interrupt Enable Command Register */
.equ AIC_IDCR, (292) /* Interrupt Disable Command Register */
.equ AIC_ICCR, (296) /* Interrupt Clear Command Register */
.equ AIC_ISCR, (300) /* Interrupt Set Command Register */
.equ AIC_EOICR, (304) /* End of Interrupt Command Register */
.equ AIC_SPU, (308) /* Spurious Vector Register */
.equ AIC_DCR, (312) /* Debug Control Register (Protect) */
.equ AIC_FFER, (320) /* Fast Forcing Enable Register */
.equ AIC_FFDR, (324) /* Fast Forcing Disable Register */
.equ AIC_FFSR, (328) /* Fast Forcing Status Register */
# -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
.equ AT91C_AIC_PRIOR, (0x7 << 0) /* (AIC) Priority Level */
.equ AT91C_AIC_PRIOR_LOWEST, (0x0) /* (AIC) Lowest priority level */
.equ AT91C_AIC_PRIOR_HIGHEST, (0x7) /* (AIC) Highest priority level */
.equ AT91C_AIC_SRCTYPE, (0x3 << 5) /* (AIC) Interrupt Source Type */
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