evmdm642_aic23_setfreq.c

DM642串口调试模块

/*
 *  Copyright 2003 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 */

/*
 *  ======== evmdm642_aic23_setfreq.c ========
 *  EVMDM642_AIC23_setFreq() implementation
 */
 
#include <evmdm642.h>
#include <evmdm642_aic23.h>
#include <evmdm642_apll.h>

/* Table of supported frequencies */
static Uint16 freqtable[] = 
{
    EVMDM642_AIC23_FREQ_8KHZ,  0x06,  // 8000 Hz
    EVMDM642_AIC23_FREQ_16KHZ, 0x2c,  // 16000 Hz
    EVMDM642_AIC23_FREQ_24KHZ, 0x20,  // 24000 Hz
    EVMDM642_AIC23_FREQ_32KHZ, 0x0c,  // 32000 Hz
    EVMDM642_AIC23_FREQ_44KHZ, 0x11,  // 44100 Hz
    EVMDM642_AIC23_FREQ_48KHZ, 0x00,  // 48000 Hz
    EVMDM642_AIC23_FREQ_96KHZ, 0x0e,  // 96000 Hz
    0, 0                             // End of table
};

/*
 *  ======== EVMDM642_AIC23_setFreq ========
 *  Set the codec sample rate frequency
 */
void EVMDM642_AIC23_setFreq(EVMDM642_AIC23_CodecHandle hCodec, Uint32 freq)
{
    Uint16 regval, curr;
    
    /* Calculate codec clock control setting, assume USB Mode (12MHz) */
    /* regval will contain CLKIN,SR3..SR0,BOSR */
    curr = 0;
    while(1)
    {
        /* Do nothing if frequency doesn't match */
        if (freqtable[curr] == 0)
            return;

        /* Check for match */            
        if (freqtable[curr] == freq)
        {
            regval = freqtable[curr + 1];
            break;
        }
            
        /* Set up for next pair */
        curr += 2;
    }
    
    /* Set APLL to correct frequency range */
    if (freq == EVMDM642_AIC23_FREQ_44KHZ)
        EVMDM642_APLL_rset(EVMDM642_APLL_FSG1);
    else
        EVMDM642_APLL_rset(EVMDM642_APLL_FSG0);
    
    /* Write to codec register */
    EVMDM642_AIC23_rset(hCodec, EVMDM642_AIC23_SAMPLERATE,
        (EVMDM642_AIC23_rget(hCodec, EVMDM642_AIC23_SAMPLERATE) & 0xff81) |
        ((regval & 0x3f) << 1));
}