dma4.c

使用在TI 系列dsk5402 的很多可用例子

    MCBSP_XCR2_XCOMPAND_DEFAULT,
    MCBSP_XCR2_XFIG_YES,
    MCBSP_XCR2_XDATDLY_1BIT
  ),                                     /* XCR2  */
  MCBSP_SRGR1_RMK(
    MCBSP_SRGR1_FWID_OF(0),
    MCBSP_SRGR1_CLKGDV_OF(0)
  ),                                     /* SRGR1 */
  MCBSP_SRGR2_RMK(
    MCBSP_SRGR2_GSYNC_FREE,
    MCBSP_SRGR2_CLKSP_RISING,
    MCBSP_SRGR2_CLKSM_INTERNAL,
    MCBSP_SRGR2_FSGM_DXR2XSR,
    MCBSP_SRGR2_FPER_OF(0)
  ),                                     /* SRGR2 */
  0x0000u,                               /* MCR1  */
  0x0000u,                               /* MCR2  */
  MCBSP_PCR_RMK(
       MCBSP_PCR_XIOEN_DEFAULT,      
       MCBSP_PCR_RIOEN_DEFAULT,      
       MCBSP_PCR_FSXM_INTERNAL,      
       MCBSP_PCR_FSRM_DEFAULT,       
       MCBSP_PCR_CLKXM_OUTPUT,       
       MCBSP_PCR_CLKRM_DEFAULT,      
       MCBSP_PCR_FSXP_DEFAULT,       
       MCBSP_PCR_FSRP_DEFAULT,       
       MCBSP_PCR_CLKXP_DEFAULT,      
       MCBSP_PCR_CLKRP_DEFAULT
  ),                                     /* PCR   */
  0x0000u,                               /* RCERA */
  0x0000u,                               /* RCERB */
  0x0000u,                               /* XCERA */
  0x0000u,                               /* XCERB */
};

   

/* Create a configuration structure for DMa channel 3 using */
/* predefined CSL macros and symbolic constants             */                           
DMA_Config  my_dmaConfigCha3 = {
  0,                               /* Priority */ 
  DMA_DMMCR_RMK(
    DMA_DMMCR_AUTOINIT_OFF,
    DMA_DMMCR_DINM_ON,
    DMA_DMMCR_IMOD_FULL_ONLY,
    DMA_DMMCR_CTMOD_ABU,
    DMA_DMMCR_SIND_DMIDX0,
    DMA_DMMCR_DMS_DATA,
    DMA_DMMCR_DIND_NOMOD,
    DMA_DMMCR_DMD_DATA
  ),                               /* DMMCR */ 
  DMA_DMSFC_RMK(
    DMA_DMSFC_DSYN_XEVT0,
    DMA_DMSFC_DBLW_OFF,
    DMA_DMSFC_FRAMECNT_OF(0)
  ),                               /* DMSFC */
  (DMA_AdrPtr)&src[1],             /* DMSRC */
  (DMA_AdrPtr)MCBSP_ADDR(DXR10),   /* DMDST */
  (Uint16)(N)                      /* DMCTR = buffsize */
};

/* Create configuration structure for DMA channel 2 using */
/* predefined CSL macros and symbolic constants           */
DMA_Config  my_dmaConfigCha2 = {
  1,                              /* Set Priority */ 
  DMA_DMMCR_RMK(
    DMA_DMMCR_AUTOINIT_OFF,
    DMA_DMMCR_DINM_ON,
    DMA_DMMCR_IMOD_FULL_ONLY,
    DMA_DMMCR_CTMOD_ABU,
    DMA_DMMCR_SIND_NOMOD,
    DMA_DMMCR_DMS_DATA,
    DMA_DMMCR_DIND_DMIDX0,
    DMA_DMMCR_DMD_DATA
  ),                              /* DMMCR */ 
  DMA_DMSFC_RMK(
    DMA_DMSFC_DSYN_REVT0,
    DMA_DMSFC_DBLW_OFF,
    DMA_DMSFC_FRAMECNT_OF(0)
  ),                              /* DMSFC */
  (DMA_AdrPtr)MCBSP_ADDR(DRR10),  /* DMSRC */
  (DMA_AdrPtr)&dst[0],            /* DMDST */
  (Uint16)(N)                     /* DMCTR = buffsize */
};

/* Global declarations */
DMA_Handle myhDmaCha2;
DMA_Handle myhDmaCha3;
volatile Bool WaitForDma = TRUE;
void dmaCha3Isr(void);
void dmaCha2Isr(void);

/*----------------------------------------------------------------------------*/
void main() {
  Uint16 i;
  
  /* Initialize CSL library, this step is required */
  CSL_init();

  /* Initialize send and receive buffers */
  for (i=0; i<= N-1; i++){                        
     dst[i] = 0;       
     src[i] = i+1;
  }                                       
}

/*----------------------------------------------------------------------------*/
void taskFunc() {

  MCBSP_Handle myhMcbsp;
  Uint16 err = 0;
  Uint16 cha2EventId, cha3EventId;
  Uint16 i;
  int old_intm;  


  LOG_printf(&LogMain,"<DMA4>");

  /* Temporarily disable all maskable interrupts */
  /* keeping old status of INTM bit              */
  old_intm = IRQ_globalDisable();

  /* Open MCBSP channel 0 */
  myhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET); 
  
  /* Write configuration values to MCBSP 0 control registers */
  MCBSP_config(myhMcbsp, &my_mcbspConfig);       

  /* Open DMA channels 2 & 3*/
  myhDmaCha2 = DMA_open(DMA_CHA2, 0); 
  myhDmaCha3 = DMA_open(DMA_CHA3, 0);

  /* Write configuration structure values to DMa control registers */
  DMA_config(myhDmaCha2, &my_dmaConfigCha2);      
  DMA_config(myhDmaCha3, &my_dmaConfigCha3);     

  /* Get Event ID's associated with DMA channels */
  cha2EventId = DMA_getEventId(myhDmaCha2);
  cha3EventId = DMA_getEventId(myhDmaCha3); 
 
  /* Enable mask of DMA channel 2 and 3 interrupts by setting */
  /* the interrupt selector value in DMA priority and enable  */
  /* register, DMPREC                                         */
  DMA_FSET(DMPREC,INTOSEL,DMA_DMPREC_INTOSEL_CH2_CH3);

  /* Set FREE bit in DMPREC to enable free run on DMA         */
  DMA_FSET(DMPREC,FREE,1);
  
  /* Clear all pending maskable interrupts */
  CHIP_RSET(IFR,0xFFFFu);                

  /* Enable interrupts for DMA channels 2 & 3 */
  IRQ_enable(cha2EventId);
  IRQ_enable(cha3EventId);

  /* Map DMA interrupts for use with dispatcher */
  IRQ_map(cha2EventId);
  IRQ_map(cha3EventId);

  /* Set value of Global Index Register , DMIDX0 */
  DMA_RSET(DMIDX0,1);
  
  /* Enable all maskable interrupts, INTM = 0 */
  IRQ_globalRestore(old_intm);
          
  
  /* Take MCBSP transmit and receive out of reset */  
  MCBSP_start(myhMcbsp, 
              MCBSP_RCV_START|MCBSP_XMIT_START,
              0
              );

  /* Prime MCBSP DXR */
  while(!(MCBSP_xrdy(myhMcbsp))){
    ;
  }
  MCBSP_write16(myhMcbsp,src[0]);
 
  /* Start DMA */
  DMA_start(myhDmaCha3);
  DMA_start(myhDmaCha2); 

  /* Enable all maskable interrupts, INTM = 0, INTM = 0 by default */
  /* after main() executes                                         */
  IRQ_globalRestore(old_intm);
           
  /* Start Sample Rate Generator and Enable Frame Sync */  
  MCBSP_start(myhMcbsp, 
    MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC , 
    0x100
  );
   
  /* Wait for Transfer to Complete */
  while(WaitForDma);
  
  /* Check Data to Make Sure Transfer was Succesful */
  for (i = 0; i <= N-1; i++) {
    if (dst[i] != src[i]){
      ++err; 
      break;
    }
  }

   /* We are thru with the DMA channels and the MCBSP */
   /* so close them.                                  */
   DMA_close(myhDmaCha2); 
   DMA_close(myhDmaCha3);
   MCBSP_close(myhMcbsp); 
   
   LOG_printf(&LogMain,"DATA buffered in DMA channel 3 written via DXR to be recieved via DRR into a buffer in DMA channel 2\n");
   LOG_printf(&LogMain,"%s",err? "TEST FAILED" : "TEST PASSED");
   LOG_printf(&LogMain,"<DONE>");
}

/* DMA Channel ISRs, these functions will be called by DSP/BIOS dispatcher */
/*----------------------------------------------------------------------------*/
void dmaCha3Isr(void) {
  DMA_stop(myhDmaCha3);
}

/*----------------------------------------------------------------------------*/
void dmaCha2Isr(void) {
  DMA_stop(myhDmaCha2);
  /* Transfer is complete */
  WaitForDma = FALSE;
}