dma3.c

使用在TI 系列dsk5402 的很多可用例子

    MCBSP_RCR2_RWDLEN2_DEFAULT,
    MCBSP_RCR2_RCOMPAND_DEFAULT,
    MCBSP_RCR2_RFIG_YES,
    MCBSP_RCR2_RDATDLY_1BIT
  ),                                 /* RCR2  */
  MCBSP_XCR1_RMK(
    MCBSP_XCR1_XFRLEN1_OF(0),
    MCBSP_XCR1_XWDLEN1_16BIT
  ),                                 /* XCR1  */
  MCBSP_XCR2_RMK(
    MCBSP_XCR2_XPHASE_SINGLE,
    MCBSP_XCR2_XFRLEN2_OF(0),
    MCBSP_XCR2_XWDLEN2_DEFAULT,
    MCBSP_XCR2_XCOMPAND_DEFAULT,
    MCBSP_XCR2_XFIG_YES,
    MCBSP_XCR2_XDATDLY_1BIT
  ),                                /* XCR2  */
  MCBSP_SRGR1_RMK(
    MCBSP_SRGR1_FWID_OF(0),
    MCBSP_SRGR1_CLKGDV_OF(0)
  ),                                /* SRGR1 */
  MCBSP_SRGR2_RMK(
    MCBSP_SRGR2_GSYNC_FREE,
    MCBSP_SRGR2_CLKSP_RISING,
    MCBSP_SRGR2_CLKSM_INTERNAL,
    MCBSP_SRGR2_FSGM_DXR2XSR,
    MCBSP_SRGR2_FPER_OF(0)
  ),                                /* SRGR2 */
  0x0000u,                          /* MCR1  */
  0x0000u,                          /* MCR2  */
  MCBSP_PCR_RMK(
    MCBSP_PCR_XIOEN_DEFAULT,          
    MCBSP_PCR_RIOEN_DEFAULT,          
    MCBSP_PCR_FSXM_INTERNAL,          
    MCBSP_PCR_FSRM_DEFAULT,           
    MCBSP_PCR_CLKXM_OUTPUT,           
    MCBSP_PCR_CLKRM_DEFAULT,          
    MCBSP_PCR_FSXP_DEFAULT,           
    MCBSP_PCR_FSRP_DEFAULT,           
    MCBSP_PCR_CLKXP_DEFAULT,         
    MCBSP_PCR_CLKRP_DEFAULT
  ),                                /* PCR   */
  0x0000u,                          /* RCERA */
  0x0000u,                          /* RCERB */
  0x0000u,                          /* XCERA */
  0x0000u                           /* XCERB */
};

                              
/* Create DMA configuration structure */
DMA_Config  my_dmaConfig = {
  1,                                /* Priority */ 
  DMA_DMMCR_RMK(
    DMA_DMMCR_AUTOINIT_OFF,
    DMA_DMMCR_DINM_ON,
    DMA_DMMCR_IMOD_BLOCK_ONLY,
    DMA_DMMCR_CTMOD_ABU,
    DMA_DMMCR_SIND_NOMOD,
    DMA_DMMCR_DMS_DATA,
    DMA_DMMCR_DIND_DMIDX0,
    DMA_DMMCR_DMD_DATA
   ),                               /* DMMCR */
   DMA_DMSFC_RMK(
     DMA_DMSFC_DSYN_REVT0,
     DMA_DMSFC_DBLW_OFF,
     DMA_DMSFC_FRAMECNT_OF(0)
   ),                               /* DMSFC */
   (DMA_AdrPtr)MCBSP_ADDR(DRR10),   /* DMSRC */
   (DMA_AdrPtr)&buffer[0],          /* DMDST */
   (Uint16)(N)                      /* DMCTR = buffsize */
};

/*----------------------------------------------------------------------------*/
void main() {
  Uint16 i;

  /* Initialize CSL library, this step is required */
  CSL_init();

  /* Set IPTR to start of interrupt vector table */
  IRQ_setVecs((Uint16)(&VECSTART));

  /* Clear desitnation buffer and give source some data */
  for (i=0; i<= N-1; i++) {                    
     buffer[i] = 0; 
     src[i] = i+1;
  }  
  /* Call example function */
  taskFunc();                                               
}

/*----------------------------------------------------------------------------*/
void taskFunc(void) {

  MCBSP_Handle myhMcbsp;
  Uint16 err = 0;
  Uint16 eventId;
  int old_intm;
  Uint16 i;

  printf("<DMA3>\n");

  /* Open MCBSP port 0. This will return a MCBSP handle that can */
  /* be used in calls to other CSL, MCBSP module functions       */
  myhMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET); 
  
  /* Write configuration structure values to MCBSP control regs */
  MCBSP_config(myhMcbsp, &my_mcbspConfig);       

  /* Open DMA channel 3 */
  myhDma = DMA_open(DMA_CHA3, DMA_OPEN_RESET);    

  /* Write configuration structure values to DMA control regs */ 
  DMA_config(myhDma, &my_dmaConfig);             

  /* Request allocation for Global Index Register IDX0     */
  /* Note: this is optional.. use this function only if    */
  /* there is a potential conflict with other DMA channels */
  /* that could be using this same resource.               */
  while((DMA_globalAlloc(DMA_GBL_DMIDX0))==0);   

  /* Get Event ID associated with DMa channel 3 interrupt */
  eventId = DMA_getEventId(myhDma);      


  /* Temporarily disable all maskable interrupts */
  old_intm = IRQ_globalDisable();  
  
  /* Enable masking of DMA channel 3 interrupt in DMA */
  /* interrupt select register                        */
  DMA_FSET(DMPREC,INTOSEL,DMA_DMPREC_INTOSEL_CH2_CH3);
  
  /* Disable DMA 3 channel interrupts */
  IRQ_disable(eventId);

  /* Clear any pending DMA channel 3 interrupts */
  IRQ_clear(eventId); 
 
  /* Place ISR address at associated vector location */
  IRQ_plug(eventId, &dmaIsr);
  
  /* Enable DMA interrupt */
  IRQ_enable(eventId);              

  /* Set value of the DMA index register, DMIXD0 */
  DMA_RSET(DMIDX0,1);
  
  /* Start DMa transfer */
  DMA_start(myhDma);

  /* Enable all maskable interrupts */     
  IRQ_globalEnable();              
 
  /* Start MCBSP */ 
  MCBSP_start (
    myhMcbsp,
    MCBSP_RCV_START|MCBSP_XMIT_START|MCBSP_SRGR_START|MCBSP_SRGR_FRAMESYNC, 
    0x200
  );
  
 
  /* Send data */
  for (i=0; i<= N-1; i++) {
    /* wait for XRDY before writing next element */
    while(!MCBSP_xrdy(myhMcbsp));

    /* Write new element to DXR */               
    MCBSP_write16(myhMcbsp, src[i]);      
  }
    
  /* Wait for DMA to receive data */
  while(WaitForDma); 

  /* Check data to make sure transfer is correct */  
  for (i = 0; i <= N-1; i++) {
    if (buffer[i] != i+1) {
      ++err;
    }
  }

   /* We are thru with DMA and MCBSP, so close them */
   DMA_close(myhDma);
   MCBSP_close(myhMcbsp);
   
   /* Restore INTM to previous state */
   IRQ_globalRestore(old_intm);
 
   printf ("DMA in ABU mode. Transfer performed from serial port...\n");
   printf("%s\n",err?"TEST FAILED":"TEST PASSED");
 
}

/* DMA interrupt service routine. This function will be called by DSPBIOS dispatcher */
/*----------------------------------------------------------------------------*/
interrupt void dmaIsr(void)
{
   WaitForDma = FALSE;   
   DMA_stop(myhDma);
}