cs89x0.h

基于S3C2410的Vxworks的CS8900驱动程序源码

#define HASH_INDEX_MASK	0x0FC00

/* PP_TxEvent - Transmit Event Bit definition - Read-only */
#define TX_LOST_CRS	0x0040
#define TX_SQE_ERROR	0x0080
#define TX_OK		0x0100
#define TX_LATE_COL	0x0200
#define TX_JBR		0x0400
#define TX_16_COL	0x8000
#define TX_SEND_OK_BITS	(TX_OK|TX_LOST_CRS)
#define TX_COL_COUNT_MASK	0x7800

/* PP_BufEvent - Buffer Event Bit definition - Read-only */
#define SW_INTERRUPT	0x0040
#define RX_DMA		0x0080
#define READY_FOR_TX	0x0100
#define TX_UNDERRUN	0x0200
#define RX_MISS		0x0400
#define RX_128_BYTE	0x0800
#define TX_COL_OVRFLW	0x1000
#define RX_MISS_OVRFLW	0x2000
#define RX_DEST_MATCH	0x8000

/* PP_LineST - Ethernet Line Status bit definition - Read-only */
#define LINK_OK		0x0080
#define AUI_ON		0x0100
#define TENBASET_ON	0x0200
#define POLARITY_OK	0x1000
#define CRS_OK		0x4000

/* PP_SelfST - Chip Software Status bit definition */
#define ACTIVE_33V	0x0040
#define INIT_DONE	0x0080
#define SI_BUSY		0x0100
#define EEPROM_PRESENT	0x0200
#define EEPROM_OK	0x0400
#define EL_PRESENT	0x0800
#define EE_SIZE_64	0x1000

/* PP_BusST - ISA Bus Status bit definition */
#define TX_BID_ERROR	0x0080
#define READY_FOR_TX_NOW	0x0100

/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
#define RE_NEG_NOW	0x0040
#define ALLOW_FDX	0x0080
#define AUTO_NEG_ENABLE	0x0100
#define NLP_ENABLE	0x0200
#define FORCE_FDX	0x8000
#define AUTO_NEG_BITS	(FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
#define AUTO_NEG_MASK	(FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)

/* PP_AutoNegST - Auto Negotiation Status bit definition */
#define AUTO_NEG_BUSY	0x0080
#define FLP_LINK	0x0100
#define FLP_LINK_GOOD	0x0800
#define LINK_FAULT	0x1000
#define HDX_ACTIVE	0x4000
#define FDX_ACTIVE	0x8000

/*  The following block defines the ISQ event types */
#define ISQ_RECEIVER_EVENT	0x04
#define ISQ_TRANSMITTER_EVENT	0x08
#define ISQ_BUFFER_EVENT	0x0c
#define ISQ_RX_MISS_EVENT	0x10
#define ISQ_TX_COL_EVENT	0x12

#define ISQ_EVENT_MASK	0x003F	/*  ISQ mask to find out type of event */
#define ISQ_HIST	16	/*  small history buffer */
#define AUTOINCREMENT	0x8000	/*  Bit mask to set bit-15 for autoincrement */

#define TXRXBUFSIZE	0x0600
#define RXDMABUFSIZE	0x8000
#define RXDMASIZE	0x4000
#define TXRX_LENGTH_MASK	0x07FF

/*  rx options bits */
#define RCV_WITH_RXON	1       /*  Set SerRx ON */
#define RCV_COUNTS	2       /*  Use Framecnt1 */
#define RCV_PONG	4       /*  Pong respondent */
#define RCV_DONG	8       /*  Dong operation */
#define RCV_POLLING	0x10	/*  Poll RxEvent */
#define RCV_ISQ		0x20	/*  Use ISQ, int */
#define RCV_AUTO_DMA	0x100	/*  Set AutoRxDMAE */
#define RCV_DMA		0x200	/*  Set RxDMA only */
#define RCV_DMA_ALL	0x400	/*  Copy all DMA'ed */
#define RCV_FIXED_DATA	0x800	/*  Every frame same */
#define RCV_IO		0x1000	/*  Use ISA IO only */
#define RCV_MEMORY	0x2000	/*  Use ISA Memory */

#define RAM_SIZE	0x1000		/*  The card has 4k bytes or RAM */
#define PKT_START	PP_TxFrame	/*  Start of packet RAM */

#define RX_FRAME_PORT	0x0000
#define TX_FRAME_PORT	RX_FRAME_PORT
#define TX_CMD_PORT	0x0004
#define TX_NOW		0x0000       /*  Tx packet after   5 bytes copied */
#define TX_AFTER_381	0x0049       /*  Tx packet after 381 bytes copied */
#define TX_AFTER_ALL	0x00c9       /*  Tx packet after all bytes copied */
#define TX_LEN_PORT	0x0006       /*  Why the 9 is extracted  by SW.LEE */
#define ISQ_PORT	0x0008
#define ADD_PORT	0x000A
#define DATA_PORT	0x000C

#define EEPROM_WRITE_EN		0x00F0
#define EEPROM_WRITE_DIS	0x0000
#define EEPROM_WRITE_CMD	0x0100
#define EEPROM_READ_CMD		0x0200

/*  Receive Header */
/*  Description of header of each packet in receive area of memory */
#define RBUF_EVENT_LOW	0	/*  Low byte of RxEvent - status of received frame */
#define RBUF_EVENT_HIGH	1	/*  High byte of RxEvent - status of received frame */
#define RBUF_LEN_LOW	2	/*  Length of received data - low byte */
#define RBUF_LEN_HI	3	/*  Length of received data - high byte */
#define RBUF_HEAD_LEN	4	/*  Length of this header */

#define CHIP_READ	0x1	/*  Used to mark state of the repins code (chip or dma) */
#define DMA_READ	0x2	/*  Used to mark state of the repins code (chip or dma) */

/*  for bios scan */
/*  */
#ifdef CSDEBUG
/*  use these values for debugging bios scan */
#define BIOS_START_SEG	0x00000
#define BIOS_OFFSET_INC	0x0010
#else
#define BIOS_START_SEG	0x0c000
#define BIOS_OFFSET_INC	0x0200
#endif

#define BIOS_LAST_OFFSET	0x0fc00

/*  Byte offsets into the EEPROM configuration buffer */
#define ISA_CNF_OFFSET		0x6
#define TX_CTL_OFFSET		(ISA_CNF_OFFSET + 8)	/*  8900 eeprom */
#define AUTO_NEG_CNF_OFFSET	(ISA_CNF_OFFSET + 8)	/*  8920 eeprom */

  /*  the assumption here is that the bits in the eeprom are generally  */
  /*  in the same position as those in the autonegctl register. */
  /*  Of course the IMM bit is not in that register so it must be  */
  /*  masked out */
#define EE_FORCE_FDX 		0x8000
#define EE_NLP_ENABLE		0x0200
#define EE_AUTO_NEG_ENABLE	0x0100
#define EE_ALLOW_FDX		0x0080
#define EE_AUTO_NEG_CNF_MASK	(EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)

#define IMM_BIT			0x0040	/*  ignore missing media  */

#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
#define A_CNF_10B_T		0x0001
#define A_CNF_AUI		0x0002
#define A_CNF_10B_2		0x0004
#define A_CNF_MEDIA_TYPE	0x0060
#define A_CNF_MEDIA_AUTO	0x0000
#define A_CNF_MEDIA_10B_T	0x0020
#define A_CNF_MEDIA_AUI		0x0040
#define A_CNF_MEDIA_10B_2	0x0060
#define A_CNF_DC_DC_POLARITY	0x0080
#define A_CNF_NO_AUTO_POLARITY	0x2000
#define A_CNF_LOW_RX_SQUELCH	0x4000
#define A_CNF_EXTND_10B_2	0x8000

#define PACKET_PAGE_OFFSET	0x8

/*  Bit definitions for the ISA configuration word from the EEPROM */
#define INT_NO_MASK	0x000F
#define DMA_NO_MASK	0x0070
#define ISA_DMA_SIZE	0x0200
#define ISA_AUTO_RxDMA	0x0400
#define ISA_RxDMA	0x0800
#define DMA_BURST	0x1000
#define STREAM_TRANSFER	0x2000
#define ANY_ISA_DMA	(ISA_AUTO_RxDMA | ISA_RxDMA)

/*  DMA controller registers */
#define DMA_BASE	0x00     /*  DMA controller base */
#define DMA_BASE_2	0x0C0    /*  DMA controller base */

#define DMA_STAT	0x0D0    /*  DMA controller status register */
#define DMA_MASK	0x0D4    /*  DMA controller mask register */
#define DMA_MODE	0x0D6    /*  DMA controller mode register */
#define DMA_RESETFF	0x0D8    /*  DMA controller first/last flip flop */

/*  DMA data */
#define DMA_DISABLE	0x04     /*  Disable channel n */
#define DMA_ENABLE	0x00     /*  Enable channel n */
/*  Demand transfers, incr. address, auto init, writes, ch. n */
#define DMA_RX_MODE	0x14
/*  Demand transfers, incr. address, auto init, reads, ch. n */
#define DMA_TX_MODE	0x18

#define DMA_SIZE (16*1024) /*  Size of dma buffer - 16k */

#define CS8900		0x0000
#define CS8920		0x4000   
#define CS8920M		0x6000   
#define REVISON_BITS	0x1F00
#define EEVER_NUMBER	0x12
#define CHKSUM_LEN	0x14
#define CHKSUM_VAL	0x0000
#define START_EEPROM_DATA	0x001c	/*  Offset into eeprom for start of data */
#define IRQ_MAP_EEPROM_DATA	0x0046	/*  Offset into eeprom for the IRQ map */
#define IRQ_MAP_LEN	0x0004 /*  No of bytes to read for the IRQ map */
#define PNP_IRQ_FRMT	0x0022 /*  PNP small item IRQ format */
#define CS8900_IRQ_MAP	0x1c20 /*  This IRQ map is fixed */

#define CS8920_NO_INTS	0x0F   /*  Max CS8920 interrupt select # */

#define PNP_ADD_PORT	0x0279
#define PNP_WRITE_PORT	0x0A79

#define GET_PNP_ISA_STRUCT	0x40
#define PNP_ISA_STRUCT_LEN	0x06
#define PNP_CSN_CNT_OFF		0x01
#define PNP_RD_PORT_OFF		0x02
#define PNP_FUNCTION_OK		0x00
#define PNP_WAKE		0x03
#define PNP_RSRC_DATA		0x04
#define PNP_RSRC_READY		0x01
#define PNP_STATUS		0x05
#define PNP_ACTIVATE		0x30
#define PNP_CNF_IO_H		0x60
#define PNP_CNF_IO_L		0x61
#define PNP_CNF_INT		0x70
#define PNP_CNF_DMA		0x74
#define PNP_CNF_MEM		0x48

#define BIT0			1
#define BIT15			0x8000