at91fr.h

0x ISP LPC210x的ISP软件 Ucosii 2.52 for lpc2100 uC/OS-II移植程序及相关中间件 LPC2114 component library LP

#ifndef  _AT91FR_
#define  _AT91FR_

typedef	unsigned char	BYTE;

#define	U8			unsigned char
#define	U16			unsigned short
#define	U32			unsigned int
#define	REG8		volatile unsigned char
#define	REG16		volatile unsigned short
#define	REG32		volatile unsigned int
#define	VPchar		*(REG8 *)
#define	VPshort		*(REG16 *)
#define	VPint		*(REG32 *)
#define	Pchar		(REG8 *)
#define	Pshort		(REG16 *)
#define	Pint	    (REG32 *)

#define	FLASH_BASE      (0x01000000)

// EBI User Interface
#define	EBI_BASE		0xFFE00000
#define	EBI_CSR0		(VPint(EBI_BASE))				// Chip Select Register 0
#define	EBI_CSR1		(VPint(EBI_BASE+0x04))		// Chip Select Register 1
#define	EBI_CSR2		(VPint(EBI_BASE+0x08))		// Chip Select Register 2
#define	EBI_CSR3		(VPint(EBI_BASE+0x0C))		// Chip Select Register 3
#define	EBI_CSR4		(VPint(EBI_BASE+0x10))		// Chip Select Register 4
#define	EBI_CSR5		(VPint(EBI_BASE+0x14))		// Chip Select Register 5
#define	EBI_CSR6		(VPint(EBI_BASE+0x18))		// Chip Select Register 6
#define	EBI_CSR7		(VPint(EBI_BASE+0x1C))		// Chip Select Register 7
#define	EBI_RCR			(VPint(EBI_BASE+0x20))		// Remap Control Register
#define	EBI_MCR			(VPint(EBI_BASE+0x24))		// Memory Control Register

//AIC User Interface
#define	AIC_BASE		0xFFFFF000
#define	AIC_SMR0		(VPint(AIC_BASE))  //AIC Source Mode Register
#define	AIC_SMR4		(VPint(AIC_BASE+0x10))//TC0
#define	AIC_SVR0		(VPint(AIC_BASE+0x80))  //AIC Source Vector Register
#define	AIC_SVR4		(VPint(AIC_BASE+0x90))  //TC0
#define	AIC_IVR 		(VPint(AIC_BASE+0x100))  //AIC Interrupt Vector Register
#define	AIC_FVR 		(VPint(AIC_BASE+0x104))  //AIC FIQ Vector Register
#define	AIC_ISR 		(VPint(AIC_BASE+0x108))  //AIC Interrupt Status Register
#define	AIC_IPR 		(VPint(AIC_BASE+0x10C))  //AIC Interrupt Pending Register
#define	AIC_IMR 		(VPint(AIC_BASE+0x110))  //AIC Interrupt Mask Register
#define	AIC_CISR 		(VPint(AIC_BASE+0x114))  //AIC Core Interrupt Status Register
#define	AIC_IECR 		(VPint(AIC_BASE+0x120))  //AIC Interrupt Enable Command Register
#define	AIC_IDCR		(VPint(AIC_BASE+0x124))		// AIC Disable Register
#define	AIC_ICCR		(VPint(AIC_BASE+0x128))	// AIC Interrupt Clear Command Register
#define	AIC_ISCR		(VPint(AIC_BASE+0x12C))	// AIC Interrupt Set Command Register
#define	AIC_EOICR		(VPint(AIC_BASE+0x130))	// AIC End Of Interrupt Command Register
#define	AIC_SPU		    (VPint(AIC_BASE+0x134))	// AIC Spurious Vector Register
// Peripheral Interface
#define	PS_BASE			0xFFFF4000
#define	PS_CR			(VPint(PS_BASE))				// Control Register
#define	PS_PCER			(VPint(PS_BASE+0x04))		// Peripheral Clock Enable Register
#define	PS_PCDR			(VPint(PS_BASE+0x08))		// Peripheral Clock Disable Register
#define	PS_PCSR			(VPint(PS_BASE+0x0C))		// Peripheral Clock Status Register

// Parallel IO Interface
#define	PIO_BASE		0xFFFF0000
#define	PIO_PER		(VPint(PIO_BASE))			// PIO Enable Register,use io enable
#define	PIO_PDR		(VPint(PIO_BASE+0x04))		// PIO Disable Register,use parell enable
#define	PIO_PSR		(VPint(PIO_BASE+0x08))		// PIO Status Register
#define	PIO_OER		(VPint(PIO_BASE+0x10))		// PIO Output Enable Register
#define	PIO_ODR		(VPint(PIO_BASE+0x14))		// PIO Output Disable Register
#define	PIO_OSR		(VPint(PIO_BASE+0x18))		// PIO Output Status Register
#define	PIO_SODR	(VPint(PIO_BASE+0x30))		// PIO Set Output Data Register
#define	PIO_CODR	(VPint(PIO_BASE+0x34))		// PIO Clear Output Data Register
#define	PIO_ODSR	(VPint(PIO_BASE+0x38))		// PIO Output Data StatusRegister
#define	PIO_PDSR	(VPint(PIO_BASE+0x3C))		// PIO Pin Data Status Register

// Advanced Interrupt Controller
//SF
#define SF_PMR   	(VPint(0xFFF00018))
//USART0 user interface
#define US0_BASE    0xFFFD0000
#define US0_CR      (VPint(US0_BASE))			//USART Control register
#define US0_MR      (VPint(US0_BASE+0x04))		//USART Mode register
#define US0_IER     (VPint(US0_BASE+0x08))		//USART interrupt enable register
#define US0_IDR     (VPint(US0_BASE+0x0C))		//USART interrupt disable register
#define US0_IMR     (VPint(US0_BASE+0x10))		//USART interrupt Mask register
#define US0_CSR     (VPint(US0_BASE+0x14))		//USART Channel status register
#define US0_RHR     (VPint(US0_BASE+0x18))		//USART Reciver Holding register
#define US0_THR     (VPint(US0_BASE+0x1C))		//USART Transmiter Holding register
#define US0_BRGR    (VPint(US0_BASE+0x20))		//USART Baud Rate Generator register
#define US0_RPR     (VPint(US0_BASE+0x30))		//USART Reciver Pointer register
#define US0_RCR     (VPint(US0_BASE+0x34))		//USART Reciver Couter register
#define US0_TPR     (VPint(US0_BASE+0x38))		//USART Transmiter Pointer register
#define US0_TCR     (VPint(US0_BASE+0x3C))		//USART Transmiter Couter register
//USART1 user interface
#define US1_BASE    0xFFFCC000
#define US1_CR      (VPint(US1_BASE))			//USART Control register
#define US1_MR      (VPint(US1_BASE+0x04))		//USART Mode register
#define US1_IER     (VPint(US1_BASE+0x08))		//USART interrupt enable register
#define US1_IDR     (VPint(US1_BASE+0x0C))		//USART interrupt disable register
#define US1_IMR     (VPint(US1_BASE+0x10))		//USART interrupt Mask register
#define US1_CSR     (VPint(US1_BASE+0x14))		//USART Channel status register
#define US1_RHR     (VPint(US1_BASE+0x18))		//USART Reciver Holding register
#define US1_THR     (VPint(US1_BASE+0x1C))		//USART Transmiter Holding register
#define US1_BRGR    (VPint(US1_BASE+0x20))		//USART Baud Rate Generator register
#define US1_RPR     (VPint(US1_BASE+0x30))		//USART Reciver Pointer register
#define US1_RCR     (VPint(US1_BASE+0x34))		//USART Reciver Couter register
#define US1_TPR     (VPint(US1_BASE+0x38))		//USART Transmiter Pointer register
#define US1_TCR     (VPint(US1_BASE+0x3C))		//USART Transmiter Couter register

//TC User interface
#define TC_BASE		0xFFFE0000
#define TC_BCR   	(VPint(TC_BASE+0xC0))		//TC Block Control Register
#define TC_BMR   	(VPint(TC_BASE+0xC4))		//TC Block Mode Register
#define TC0_CCR     (VPint(TC_BASE))			//TC0 Channel Control Register(w)
#define TC0_CMR     (VPint(TC_BASE+0x04))		//TC0 Channel Mode Register
#define TC0_CVR     (VPint(TC_BASE+0x10))		//TC0 Counter Value Register
#define TC0_RA      (VPint(TC_BASE+0x14))		//TC0 Register A
#define TC0_RB      (VPint(TC_BASE+0x18))		//TC0 Register B
#define TC0_RC      (VPint(TC_BASE+0x1C))		//TC0 Register C/
#define TC0_SR      (VPint(TC_BASE+0x20))		//TC0 Status Register
#define TC0_IER     (VPint(TC_BASE+0x24))		//TC0 Interrupt Enable Register
#define TC0_IDR     (VPint(TC_BASE+0x28))		//TC0 Interrupt Disable Register
#define TC0_IMR     (VPint(TC_BASE+0x2C))		//TC0 Interrupt Mask Register

#define EBI_CSR_0   ((unsigned int )(FLASH_BASE | 0x2539))     // 0x01000000, 16MB, 2 tdf, 16 bits, 7 WS


#endif