muxcntlr.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 10 15:38:47 2005 " "Info: Processing started: Thu Nov 10 15:38:47 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off muxcntlr -c muxcntlr " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off muxcntlr -c muxcntlr" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "muxcntlr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file muxcntlr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 muxcntlr-behavior_muxcntlr " "Info: Found design unit 1: muxcntlr-behavior_muxcntlr" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 105 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 muxcntlr " "Info: Found entity 1: muxcntlr" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "muxcntlr " "Info: Elaborating entity \"muxcntlr\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "V33_UART_RXD1 " "Warning: No output dependent on input pin \"V33_UART_RXD1\"" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 79 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SPAREIO1 " "Warning: No output dependent on input pin \"SPAREIO1\"" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 83 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SPAREIO2 " "Warning: No output dependent on input pin \"SPAREIO2\"" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 84 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SPAREIO3 " "Warning: No output dependent on input pin \"SPAREIO3\"" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 85 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "96 " "Info: Implemented 96 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "30 " "Info: Implemented 30 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 10 15:38:49 2005 " "Info: Processing ended: Thu Nov 10 15:38:49 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}