⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 muxcntlr.fit.qmsg

📁 CPLD源码 达芬奇开发套件 很好 <没找到!> 查询更多词典 搜索因特网
💻 QMSG
字号:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 10 15:38:51 2005 " "Info: Processing started: Thu Nov 10 15:38:51 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "muxcntlr EPM240GT100C3 " "Info: Selected device EPM240GT100C3 for design \"muxcntlr\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570GT100C3 " "Info: Device EPM570GT100C3 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "V33_TIMER_IN Global clock in PIN 62 " "Info: Automatically promoted signal \"V33_TIMER_IN\" to use Global clock in PIN 62" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 81 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.469 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 6.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns ATA_SEL 1 PIN PIN_54 14 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_54; Fanout = 14; PIN Node = 'ATA_SEL'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { ATA_SEL } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 89 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.214 ns) + CELL(0.125 ns) 3.047 ns V18_EM_DATA_BUF_EN~191 2 COMB LAB_X2_Y4 1 " "Info: 2: + IC(2.214 ns) + CELL(0.125 ns) = 3.047 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_EN~191'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.339 ns" { ATA_SEL V18_EM_DATA_BUF_EN~191 } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.462 ns) 3.786 ns V18_EM_DATA_BUF_EN~193 3 COMB LAB_X2_Y4 1 " "Info: 3: + IC(0.277 ns) + CELL(0.462 ns) = 3.786 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_EN~193'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "0.739 ns" { V18_EM_DATA_BUF_EN~191 V18_EM_DATA_BUF_EN~193 } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(2.312 ns) 6.469 ns V18_EM_DATA_BUF_EN 4 PIN PIN_3 0 " "Info: 4: + IC(0.371 ns) + CELL(2.312 ns) = 6.469 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_EN'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.683 ns" { V18_EM_DATA_BUF_EN~193 V18_EM_DATA_BUF_EN } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.607 ns 55.76 % " "Info: Total cell delay = 3.607 ns ( 55.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.862 ns 44.24 % " "Info: Total interconnect delay = 2.862 ns ( 44.24 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "6.469 ns" { ATA_SEL V18_EM_DATA_BUF_EN~191 V18_EM_DATA_BUF_EN~193 V18_EM_DATA_BUF_EN } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 10 15:38:52 2005 " "Info: Processing ended: Thu Nov 10 15:38:52 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -