muxcntlr.csf.qmsg

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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off muxcntlr -c muxcntlr " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off muxcntlr -c muxcntlr" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EPM240T100C3 " "Warning: Timing characteristics of device EPM240T100C3 are preliminary" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "V33_CF_PWR_ON V18_EM_DATA_BUF_EN 5.230 ns Longest " "Info: Longest tpd from source pin V33_CF_PWR_ON to destination pin V18_EM_DATA_BUF_EN is 5.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns V33_CF_PWR_ON 1 PIN IOC_X8_Y1_N3 11 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = IOC_X8_Y1_N3; Fanout = 11; PIN Node = 'V33_CF_PWR_ON'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_PWR_ON } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 87 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.582 ns) 2.520 ns i81~8 2 COMB LC_X5_Y1_N9 1 " "Info: 2: + IC(1.211 ns) + CELL(0.582 ns) = 2.520 ns; Loc. = LC_X5_Y1_N9; Fanout = 1; COMB Node = 'i81~8'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "1.793 ns" { V33_CF_PWR_ON i81~8 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 181 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(1.454 ns) 5.230 ns V18_EM_DATA_BUF_EN 3 PIN IOC_X1_Y1_N1 0 " "Info: 3: + IC(1.256 ns) + CELL(1.454 ns) = 5.230 ns; Loc. = IOC_X1_Y1_N1; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_EN'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "2.710 ns" { i81~8 V18_EM_DATA_BUF_EN } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.763 ns 52.83 % " "Info: Total cell delay = 2.763 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.467 ns 47.17 % " "Info: Total interconnect delay = 2.467 ns ( 47.17 % )" {  } {  } 0}  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "5.230 ns" { V33_CF_PWR_ON i81~8 V18_EM_DATA_BUF_EN } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "MSP430_INT_IN MSP430_INT_OUT 3.368 ns Shortest " "Info: Shortest tpd from source pin MSP430_INT_IN to destination pin MSP430_INT_OUT is 3.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns MSP430_INT_IN 1 PIN IOC_X3_Y5_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = IOC_X3_Y5_N3; Fanout = 1; PIN Node = 'MSP430_INT_IN'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { MSP430_INT_IN } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 86 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(1.454 ns) 3.368 ns MSP430_INT_OUT 2 PIN IOC_X3_Y5_N0 0 " "Info: 2: + IC(1.187 ns) + CELL(1.454 ns) = 3.368 ns; Loc. = IOC_X3_Y5_N0; Fanout = 0; PIN Node = 'MSP430_INT_OUT'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "2.641 ns" { MSP430_INT_IN MSP430_INT_OUT } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.181 ns 64.76 % " "Info: Total cell delay = 2.181 ns ( 64.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.187 ns 35.24 % " "Info: Total interconnect delay = 1.187 ns ( 35.24 % )" {  } {  } 0}  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "3.368 ns" { MSP430_INT_IN MSP430_INT_OUT } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 30 16:33:30 2005 " "Info: Processing ended: Fri Sep 30 16:33:30 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004