muxcntlr.csf.qmsg

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{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF " "Info: Statistics of I/O pins that use the same VCCIO and VREF" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "56 unused 3.30 25 31 0 " "Info: Number of I/O pins in group: 56 (unused VREF, 3.30 VCCIO, 25 input, 31 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 38 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  38 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 31 7 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 31 total pin(s) used --  7 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 25 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 25 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.755 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 4.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns WRITE_WE 1 PIN IOC_X5_Y5_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = IOC_X5_Y5_N3; Fanout = 3; PIN Node = 'WRITE_WE'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { WRITE_WE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.096 ns) + CELL(0.128 ns) 1.951 ns i76~1 2 COMB LAB_X5_Y1 2 " "Info: 2: + IC(1.096 ns) + CELL(0.128 ns) = 1.951 ns; Loc. = LAB_X5_Y1; Fanout = 2; COMB Node = 'i76~1'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "1.224 ns" { WRITE_WE i76~1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 177 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.582 ns) 2.787 ns i77~50 3 COMB LAB_X5_Y1 1 " "Info: 3: + IC(0.254 ns) + CELL(0.582 ns) = 2.787 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'i77~50'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "0.836 ns" { i76~1 i77~50 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 175 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(1.454 ns) 4.755 ns V18_EM_DATA_BUF_DIR 4 PIN IOC_X5_Y0_N2 0 " "Info: 4: + IC(0.514 ns) + CELL(1.454 ns) = 4.755 ns; Loc. = IOC_X5_Y0_N2; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_DIR'" {  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "1.968 ns" { i77~50 V18_EM_DATA_BUF_DIR } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.891 ns 60.80 % " "Info: Total cell delay = 2.891 ns ( 60.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.864 ns 39.20 % " "Info: Total interconnect delay = 1.864 ns ( 39.20 % )" {  } {  } 0}  } { { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "4.755 ns" { WRITE_WE i76~1 i77~50 V18_EM_DATA_BUF_DIR } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "8 " "Info: Estimated interconnect usage is 8% of the available device resources" {  } {  } 0}