muxcntlr.csf.qmsg

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{ "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C3 " "Info: Device EPM570T100C3 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "56 56 " "Info: No exact pin location assignment(s) for 56 pins of 56 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "UART_RXD1_DMARQ " "Info: Pin UART_RXD1_DMARQ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 34 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RXD1_DMARQ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { UART_RXD1_DMARQ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { UART_RXD1_DMARQ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "WAIT_BUSY " "Info: Pin WAIT_BUSY not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 36 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "WAIT_BUSY" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { WAIT_BUSY } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { WAIT_BUSY } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V18_EM_DATA_BUF_DIR " "Info: Pin V18_EM_DATA_BUF_DIR not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 37 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V18_EM_DATA_BUF_DIR" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V18_EM_DATA_BUF_DIR } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V18_EM_DATA_BUF_DIR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V18_EM_DATA_BUF_EN " "Info: Pin V18_EM_DATA_BUF_EN not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 38 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V18_EM_DATA_BUF_EN" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V18_EM_DATA_BUF_EN } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V18_EM_DATA_BUF_EN } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "INTRQ_EM_RNW " "Info: Pin INTRQ_EM_RNW not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 41 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "INTRQ_EM_RNW" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { INTRQ_EM_RNW } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { INTRQ_EM_RNW } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "MSP430_INT_OUT " "Info: Pin MSP430_INT_OUT not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 42 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSP430_INT_OUT" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { MSP430_INT_OUT } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { MSP430_INT_OUT } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_ALE_EM_A1 " "Info: Pin V33_SM_ALE_EM_A1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 45 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_ALE_EM_A1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_ALE_EM_A1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_ALE_EM_A1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_CLE_EM_A2 " "Info: Pin V33_SM_CLE_EM_A2 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 46 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_CLE_EM_A2" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_CLE_EM_A2 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_CLE_EM_A2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_WRITE_WE " "Info: Pin V33_SM_WRITE_WE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 47 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_WRITE_WE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_WRITE_WE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_WRITE_WE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_READ_OE " "Info: Pin V33_SM_READ_OE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 48 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_READ_OE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_READ_OE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_READ_OE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_SM_CEZ " "Info: Pin V33_SM_SM_CEZ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 49 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_SM_CEZ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_SM_CEZ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_SM_CEZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_WRITE_WE " "Info: Pin V33_CF_WRITE_WE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 55 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_WRITE_WE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_WRITE_WE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_WRITE_WE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_READ_OE " "Info: Pin V33_CF_READ_OE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 56 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_READ_OE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_READ_OE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_READ_OE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_ATA_CS0 " "Info: Pin V33_CF_ATA_CS0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 57 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_ATA_CS0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_ATA_CS0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_ATA_CS0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_ATA_CS1 " "Info: Pin V33_CF_ATA_CS1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 58 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_ATA_CS1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_ATA_CS1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_ATA_CS1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_ATA0_EM_BA0 " "Info: Pin V33_CF_ATA0_EM_BA0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 59 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_ATA0_EM_BA0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_ATA0_EM_BA0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_ATA0_EM_BA0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_ATA1_EM_BA1 " "Info: Pin V33_CF_ATA1_EM_BA1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 60 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_ATA1_EM_BA1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_ATA1_EM_BA1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_ATA1_EM_BA1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_ATA2_EM_A0 " "Info: Pin V33_CF_ATA2_EM_A0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 61 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_ATA2_EM_A0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_ATA2_EM_A0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_ATA2_EM_A0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DA0 " "Info: Pin V33_ATA_DA0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 66 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DA0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DA0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DA0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DA1 " "Info: Pin V33_ATA_DA1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 67 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DA1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DA1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DA1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DA2 " "Info: Pin V33_ATA_DA2 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 68 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DA2" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DA2 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DA2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DMACK " "Info: Pin V33_ATA_DMACK not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 69 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DMACK" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DMACK } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DMACK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_CS0 " "Info: Pin V33_ATA_CS0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 70 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_CS0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_CS0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_CS0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_CS1 " "Info: Pin V33_ATA_CS1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 71 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_CS1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_CS1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_CS1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DIOR " "Info: Pin V33_ATA_DIOR not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 72 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DIOR" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DIOR } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DIOR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DIOW " "Info: Pin V33_ATA_DIOW not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 73 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DIOW" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DIOW } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DIOW } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_BUFF_DIR " "Info: Pin V33_ATA_BUFF_DIR not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 74 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_BUFF_DIR" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_BUFF_DIR } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_BUFF_DIR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_BUFF_ENZ " "Info: Pin V33_ATA_BUFF_ENZ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 75 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_BUFF_ENZ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_BUFF_ENZ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_BUFF_ENZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_RESETn " "Info: Pin V33_ATA_RESETn not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 76 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_RESETn" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_RESETn } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_RESETn } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SYS_RESETZ " "Info: Pin V33_SYS_RESETZ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 78 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SYS_RESETZ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SYS_RESETZ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SYS_RESETZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_UART_TXD1 " "Info: Pin V33_UART_TXD1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 80 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_UART_TXD1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_UART_TXD1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_UART_TXD1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_UART_RXD1 " "Info: Pin V33_UART_RXD1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 79 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_UART_RXD1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_UART_RXD1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_UART_RXD1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_DMARQ " "Info: Pin V33_ATA_DMARQ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 63 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_DMARQ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_DMARQ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_DMARQ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA_SEL " "Info: Pin ATA_SEL not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 84 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA_SEL" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA_SEL } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA_SEL } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_CEZ " "Info: Pin V33_SM_CEZ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 82 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_CEZ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_CEZ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_CEZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "WRITE_WE " "Info: Pin WRITE_WE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 27 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "WRITE_WE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { WRITE_WE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { WRITE_WE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_PWR_ON " "Info: Pin V33_CF_PWR_ON not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 87 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_PWR_ON" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_PWR_ON } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_PWR_ON } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CFN_SEL " "Info: Pin CFN_SEL not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 83 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CFN_SEL" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { CFN_SEL } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { CFN_SEL } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA_DIR " "Info: Pin ATA_DIR not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 29 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA_DIR" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA_DIR } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA_DIR } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "EM_CS2 " "Info: Pin EM_CS2 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 35 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "EM_CS2" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { EM_CS2 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { EM_CS2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "MSP430_INT_IN " "Info: Pin MSP430_INT_IN not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 86 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSP430_INT_IN" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { MSP430_INT_IN } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { MSP430_INT_IN } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ALE_EM_A1 " "Info: Pin ALE_EM_A1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 23 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ALE_EM_A1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ALE_EM_A1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ALE_EM_A1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLE_EM_A2 " "Info: Pin CLE_EM_A2 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 22 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLE_EM_A2" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { CLE_EM_A2 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { CLE_EM_A2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "READ_OE " "Info: Pin READ_OE not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 28 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "READ_OE" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { READ_OE } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { READ_OE } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA_CS0 " "Info: Pin ATA_CS0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 31 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA_CS0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA_CS0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA_CS0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA_CS1 " "Info: Pin ATA_CS1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 30 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA_CS1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA_CS1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA_CS1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA0_EM_BA0 " "Info: Pin ATA0_EM_BA0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 26 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA0_EM_BA0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA0_EM_BA0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA0_EM_BA0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA1_EM_BA1 " "Info: Pin ATA1_EM_BA1 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 25 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA1_EM_BA1" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA1_EM_BA1 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA1_EM_BA1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ATA2_EM_A0 " "Info: Pin ATA2_EM_A0 not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 24 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "ATA2_EM_A0" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { ATA2_EM_A0 } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { ATA2_EM_A0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "UART_TXD1_DMACK " "Info: Pin UART_TXD1_DMACK not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 33 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TXD1_DMACK" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { UART_TXD1_DMACK } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { UART_TXD1_DMACK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V18_SYS_RESETZ " "Info: Pin V18_SYS_RESETZ not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 39 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V18_SYS_RESETZ" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V18_SYS_RESETZ } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V18_SYS_RESETZ } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_SM_WAIT_BUSY " "Info: Pin V33_SM_WAIT_BUSY not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 51 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_SM_WAIT_BUSY" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_SM_WAIT_BUSY } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_SM_WAIT_BUSY } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_WAIT_BUSY " "Info: Pin V33_ATA_WAIT_BUSY not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 65 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_WAIT_BUSY" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_WAIT_BUSY } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_WAIT_BUSY } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_WAIT_BUSY " "Info: Pin V33_CF_WAIT_BUSY not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 54 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_WAIT_BUSY" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_WAIT_BUSY } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_WAIT_BUSY } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_ATA_INTRQ_EM_RNW " "Info: Pin V33_ATA_INTRQ_EM_RNW not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 64 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_ATA_INTRQ_EM_RNW" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_ATA_INTRQ_EM_RNW } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_ATA_INTRQ_EM_RNW } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "V33_CF_INTRQ_EM_RNW " "Info: Pin V33_CF_INTRQ_EM_RNW not assigned to an exact location on the device" {  } { { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" "" "" { Text "c:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd" 53 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "V33_CF_INTRQ_EM_RNW" } } } } { "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" "" "" { Report "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "c:/fpga/davinci_evm/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "" "" "" { V33_CF_INTRQ_EM_RNW } "NODE_NAME" } } } { "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { Floorplan "c:/fpga/davinci_evm/muxcntlr/muxcntlr.fld" "" "" { V33_CF_INTRQ_EM_RNW } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_AND_IO_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing tsu, tco, tpd and all clocks equally to maximize operation frequency and I/O performance" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP Scan-chain Inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}