muxcntlr.tan.qmsg

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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "V33_TIMER_IN register register div8\[1\] div8\[2\] 304.04 MHz Internal " "Info: Clock \"V33_TIMER_IN\" Internal fmax is restricted to 304.04 MHz between source register \"div8\[1\]\" and destination register \"div8\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.121 ns + Longest register register " "Info: + Longest register to register delay is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div8\[1\] 1 REG LC_X5_Y1_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; REG Node = 'div8\[1\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { div8[1] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.125 ns) 0.932 ns add~38 2 COMB LC_X4_Y1_N8 1 " "Info: 2: + IC(0.807 ns) + CELL(0.125 ns) = 0.932 ns; Loc. = LC_X4_Y1_N8; Fanout = 1; COMB Node = 'add~38'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "0.932 ns" { div8[1] add~38 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.777 ns) 2.121 ns div8\[2\] 3 REG LC_X4_Y1_N6 2 " "Info: 3: + IC(0.412 ns) + CELL(0.777 ns) = 2.121 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8\[2\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "1.189 ns" { add~38 div8[2] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.902 ns 42.53 % " "Info: Total cell delay = 0.902 ns ( 42.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.219 ns 57.47 % " "Info: Total interconnect delay = 1.219 ns ( 57.47 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.121 ns" { div8[1] add~38 div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.121 ns" { div8[1] add~38 div8[2] } { 0.000ns 0.807ns 0.412ns } { 0.000ns 0.125ns 0.777ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "V33_TIMER_IN destination 2.162 ns + Shortest register " "Info: + Shortest clock path from clock \"V33_TIMER_IN\" to destination register is 2.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns V33_TIMER_IN 1 CLK PIN_62 3 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { V33_TIMER_IN } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.574 ns) 2.162 ns div8\[2\] 2 REG LC_X4_Y1_N6 2 " "Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8\[2\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "1.435 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 60.18 % " "Info: Total cell delay = 1.301 ns ( 60.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 39.82 % " "Info: Total interconnect delay = 0.861 ns ( 39.82 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[2] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "V33_TIMER_IN source 2.162 ns - Longest register " "Info: - Longest clock path from clock \"V33_TIMER_IN\" to source register is 2.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns V33_TIMER_IN 1 CLK PIN_62 3 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { V33_TIMER_IN } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.574 ns) 2.162 ns div8\[1\] 2 REG LC_X5_Y1_N1 2 " "Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; REG Node = 'div8\[1\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "1.435 ns" { V33_TIMER_IN div8[1] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 60.18 % " "Info: Total cell delay = 1.301 ns ( 60.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 39.82 % " "Info: Total interconnect delay = 0.861 ns ( 39.82 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[1] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } }  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[2] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } } { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[1] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.121 ns" { div8[1] add~38 div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.121 ns" { div8[1] add~38 div8[2] } { 0.000ns 0.807ns 0.412ns } { 0.000ns 0.125ns 0.777ns } } } { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[2] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } } { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[1] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } }  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { div8[2] } {  } {  } } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "V33_TIMER_IN CPLD_TIMER_OUT div8\[2\] 5.193 ns register " "Info: tco from clock \"V33_TIMER_IN\" to destination pin \"CPLD_TIMER_OUT\" through register \"div8\[2\]\" is 5.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "V33_TIMER_IN source 2.162 ns + Longest register " "Info: + Longest clock path from clock \"V33_TIMER_IN\" to source register is 2.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns V33_TIMER_IN 1 CLK PIN_62 3 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { V33_TIMER_IN } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.574 ns) 2.162 ns div8\[2\] 2 REG LC_X4_Y1_N6 2 " "Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8\[2\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "1.435 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns 60.18 % " "Info: Total cell delay = 1.301 ns ( 60.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns 39.82 % " "Info: Total interconnect delay = 0.861 ns ( 39.82 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[2] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.796 ns + Longest register pin " "Info: + Longest register to pin delay is 2.796 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div8\[2\] 1 REG LC_X4_Y1_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8\[2\]'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { div8[2] } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 121 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.484 ns) + CELL(2.312 ns) 2.796 ns CPLD_TIMER_OUT 2 PIN PIN_37 0 " "Info: 2: + IC(0.484 ns) + CELL(2.312 ns) = 2.796 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'CPLD_TIMER_OUT'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.796 ns" { div8[2] CPLD_TIMER_OUT } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.312 ns 82.69 % " "Info: Total cell delay = 2.312 ns ( 82.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.484 ns 17.31 % " "Info: Total interconnect delay = 0.484 ns ( 17.31 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.796 ns" { div8[2] CPLD_TIMER_OUT } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.796 ns" { div8[2] CPLD_TIMER_OUT } { 0.000ns 0.484ns } { 0.000ns 2.312ns } } }  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.162 ns" { V33_TIMER_IN div8[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.162 ns" { V33_TIMER_IN V33_TIMER_IN~combout div8[2] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 0.727ns 0.574ns } } } { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.796 ns" { div8[2] CPLD_TIMER_OUT } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.796 ns" { div8[2] CPLD_TIMER_OUT } { 0.000ns 0.484ns } { 0.000ns 2.312ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ATA_SEL V18_EM_DATA_BUF_DIR 6.724 ns Longest " "Info: Longest tpd from source pin \"ATA_SEL\" to destination pin \"V18_EM_DATA_BUF_DIR\" is 6.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns ATA_SEL 1 PIN PIN_54 14 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_54; Fanout = 14; PIN Node = 'ATA_SEL'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "" { ATA_SEL } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 89 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.022 ns) + CELL(0.125 ns) 2.855 ns V18_EM_DATA_BUF_DIR~68 2 COMB LC_X3_Y4_N9 2 " "Info: 2: + IC(2.022 ns) + CELL(0.125 ns) = 2.855 ns; Loc. = LC_X3_Y4_N9; Fanout = 2; COMB Node = 'V18_EM_DATA_BUF_DIR~68'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.147 ns" { ATA_SEL V18_EM_DATA_BUF_DIR~68 } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.125 ns) 4.001 ns V18_EM_DATA_BUF_DIR~69 3 COMB LC_X2_Y4_N2 1 " "Info: 3: + IC(1.021 ns) + CELL(0.125 ns) = 4.001 ns; Loc. = LC_X2_Y4_N2; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_DIR~69'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "1.146 ns" { V18_EM_DATA_BUF_DIR~68 V18_EM_DATA_BUF_DIR~69 } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(2.312 ns) 6.724 ns V18_EM_DATA_BUF_DIR 4 PIN PIN_2 0 " "Info: 4: + IC(0.411 ns) + CELL(2.312 ns) = 6.724 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_DIR'" {  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "2.723 ns" { V18_EM_DATA_BUF_DIR~69 V18_EM_DATA_BUF_DIR } "NODE_NAME" } "" } } { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.270 ns 48.63 % " "Info: Total cell delay = 3.270 ns ( 48.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.454 ns 51.37 % " "Info: Total interconnect delay = 3.454 ns ( 51.37 % )" {  } {  } 0}  } { { "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" "" { Report "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr_cmp.qrpt" Compiler "muxcntlr" "UNKNOWN" "V1" "C:/altera/davincievm_gamma2/muxcntlr/db/muxcntlr.quartus_db" { Floorplan "C:/altera/davincievm_gamma2/muxcntlr/" "" "6.724 ns" { ATA_SEL V18_EM_DATA_BUF_DIR~68 V18_EM_DATA_BUF_DIR~69 V18_EM_DATA_BUF_DIR } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "6.724 ns" { ATA_SEL ATA_SEL~combout V18_EM_DATA_BUF_DIR~68 V18_EM_DATA_BUF_DIR~69 V18_EM_DATA_BUF_DIR } { 0.000ns 0.000ns 2.022ns 1.021ns 0.411ns } { 0.000ns 0.708ns 0.125ns 0.125ns 2.312ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 10 15:38:56 2005 " "Info: Processing ended: Thu Nov 10 15:38:56 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}