muxcntlr.tan.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 10 15:38:55 2005 " "Info: Processing started: Thu Nov 10 15:38:55 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "V33_TIMER_IN " "Info: Assuming node \"V33_TIMER_IN\" is an undefined clock" {  } { { "muxcntlr.vhd" "" { Text "C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd" 81 -1 0 } } { "c:/altera/quartus50sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50sp1/bin/Assignment Editor.qase" 1 { { 0 "V33_TIMER_IN" } } } }  } 0}  } {  } 0}