muxcntlr.flow.rpt

CPLD源码 达芬奇开发套件 很好 <没找到!> 查询更多词典 搜索因特网

Flow report for muxcntlr
Thu Nov 10 15:38:58 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Flow Summary                                                           ;
+-------------------------+----------------------------------------------+
; Flow Status             ; Successful - Thu Nov 10 15:38:58 2005        ;
; Quartus II Version      ; 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition ;
; Revision Name           ; muxcntlr                                     ;
; Top-level Entity Name   ; muxcntlr                                     ;
; Family                  ; MAX II                                       ;
; Device                  ; EPM240GT100C3                                ;
; Timing Models           ; Final                                        ;
; Met timing requirements ; Yes                                          ;
; Total logic elements    ; 34 / 240 ( 14 % )                            ;
; Total pins              ; 62 / 80 ( 77 % )                             ;
; Total virtual pins      ; 0                                            ;
; UFM blocks              ; 0 / 1 ( 0 % )                                ;
+-------------------------+----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 11/10/2005 15:38:47 ;
; Main task         ; Compilation         ;
; Revision Name     ; muxcntlr            ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:02     ;
; Fitter               ; 00:00:02     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:01     ;
; EDA Netlist Writer   ; 00:00:01     ;
; Total                ; 00:00:07     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off muxcntlr -c muxcntlr
quartus_fit --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr
quartus_asm --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr
quartus_tan --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr
quartus_eda --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr