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	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => ATA2_EM_A0_acombout,
	datad => CFN_SEL_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_ATA2_EM_A0_a12);

V33_ATA_DA0_a10_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DA0_a10 = !ATA_SEL_acombout & ATA0_EM_BA0_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => ATA0_EM_BA0_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DA0_a10);

V33_ATA_DA1_a10_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DA1_a10 = !ATA_SEL_acombout & ATA1_EM_BA1_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => ATA1_EM_BA1_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DA1_a10);

V33_ATA_DA2_a10_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DA2_a10 = !ATA_SEL_acombout & ATA2_EM_A0_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => ATA2_EM_A0_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DA2_a10);

V33_ATA_DMACK_a3_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DMACK_a3 = ATA_SEL_acombout # UART_TXD1_DMACK_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => UART_TXD1_DMACK_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DMACK_a3);

V33_ATA_CS0_a3_I : maxii_lcell
-- Equation(s):
-- V33_ATA_CS0_a3 = ATA_SEL_acombout # ATA_CS0_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => ATA_CS0_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_CS0_a3);

V33_ATA_CS1_a3_I : maxii_lcell
-- Equation(s):
-- V33_ATA_CS1_a3 = ATA_SEL_acombout # ATA_CS1_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => ATA_CS1_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_CS1_a3);

V33_ATA_DIOR_a3_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DIOR_a3 = ATA_SEL_acombout # READ_OE_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => READ_OE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DIOR_a3);

V33_ATA_DIOW_a3_I : maxii_lcell
-- Equation(s):
-- V33_ATA_DIOW_a3 = ATA_SEL_acombout # WRITE_WE_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => WRITE_WE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_ATA_DIOW_a3);

V18_SYS_RESETZ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V18_SYS_RESETZ,
	combout => V18_SYS_RESETZ_acombout);

UART_RXD1_DMARQ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => UART_RXD1_DMARQ_a5,
	oe => VCC,
	padio => ww_UART_RXD1_DMARQ);

WAIT_BUSY_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	datain => WAIT_BUSY_a5,
	oe => VCC,
	padio => ww_WAIT_BUSY);

V18_EM_DATA_BUF_DIR_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V18_EM_DATA_BUF_DIR_a69,
	oe => VCC,
	padio => ww_V18_EM_DATA_BUF_DIR);

V18_EM_DATA_BUF_EN_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_V18_EM_DATA_BUF_EN_a193,
	oe => VCC,
	padio => ww_V18_EM_DATA_BUF_EN);

INTRQ_EM_RNW_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	datain => INTRQ_EM_RNW_a2,
	oe => VCC,
	padio => ww_INTRQ_EM_RNW);

MSP430_INT_OUT_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => MSP430_INT_IN_acombout,
	oe => VCC,
	padio => ww_MSP430_INT_OUT);

CPLD_TIMER_OUT_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => div8_a2_a,
	oe => VCC,
	padio => ww_CPLD_TIMER_OUT);

V33_SM_ALE_EM_A1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_SM_ALE_EM_A1_a10,
	oe => VCC,
	padio => ww_V33_SM_ALE_EM_A1);

V33_SM_CLE_EM_A2_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_SM_CLE_EM_A2_a10,
	oe => VCC,
	padio => ww_V33_SM_CLE_EM_A2);

V33_SM_WRITE_WE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_SM_WRITE_WE_a3,
	oe => VCC,
	padio => ww_V33_SM_WRITE_WE);

V33_SM_READ_OE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => ALT_INV_V33_SM_READ_OE_a4,
	oe => VCC,
	padio => ww_V33_SM_READ_OE);

V33_SM_SM_CEZ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_SM_CEZ_acombout,
	oe => VCC,
	padio => ww_V33_SM_SM_CEZ);

V33_CF_WRITE_WE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_WRITE_WE_a7,
	oe => VCC,
	padio => ww_V33_CF_WRITE_WE);

V33_CF_READ_OE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_READ_OE_a7,
	oe => VCC,
	padio => ww_V33_CF_READ_OE);

V33_CF_ATA_CS0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_ATA_CS0_a7,
	oe => VCC,
	padio => ww_V33_CF_ATA_CS0);

V33_CF_ATA_CS1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_ATA_CS1_a7,
	oe => VCC,
	padio => ww_V33_CF_ATA_CS1);

V33_CF_ATA0_EM_BA0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_ATA0_EM_BA0_a12,
	oe => VCC,
	padio => ww_V33_CF_ATA0_EM_BA0);

V33_CF_ATA1_EM_BA1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_ATA1_EM_BA1_a12,
	oe => VCC,
	padio => ww_V33_CF_ATA1_EM_BA1);

V33_CF_ATA2_EM_A0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_CF_ATA2_EM_A0_a12,
	oe => VCC,
	padio => ww_V33_CF_ATA2_EM_A0);

V33_ATA_DA0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DA0_a10,
	oe => VCC,
	padio => ww_V33_ATA_DA0);

V33_ATA_DA1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DA1_a10,
	oe => VCC,
	padio => ww_V33_ATA_DA1);

V33_ATA_DA2_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DA2_a10,
	oe => VCC,
	padio => ww_V33_ATA_DA2);

V33_ATA_DMACK_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DMACK_a3,
	oe => VCC,
	padio => ww_V33_ATA_DMACK);

V33_ATA_CS0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_CS0_a3,
	oe => VCC,
	padio => ww_V33_ATA_CS0);

V33_ATA_CS1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_CS1_a3,
	oe => VCC,
	padio => ww_V33_ATA_CS1);

V33_ATA_DIOR_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DIOR_a3,
	oe => VCC,
	padio => ww_V33_ATA_DIOR);

V33_ATA_DIOW_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V33_ATA_DIOW_a3,
	oe => VCC,
	padio => ww_V33_ATA_DIOW);

V33_ATA_BUFF_DIR_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => ATA_DIR_acombout,
	oe => VCC,
	padio => ww_V33_ATA_BUFF_DIR);

V33_ATA_BUFF_ENZ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => ATA_SEL_acombout,
	oe => VCC,
	padio => ww_V33_ATA_BUFF_ENZ);

V33_ATA_RESETn_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V18_SYS_RESETZ_acombout,
	oe => VCC,
	padio => ww_V33_ATA_RESETn);

V33_SYS_RESETZ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output")
-- pragma translate_on
PORT MAP (
	datain => V18_SYS_RESETZ_acombout,
	oe => VCC,
	padio => ww_V33_SYS_RESETZ);

V33_UART_RXD1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_UART_RXD1);

V33_UART_TXD1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	open_drain_output => "true")
-- pragma translate_on
PORT MAP (
	datain => VCC,
	oe => VCC,
	padio => ww_V33_UART_TXD1);

SPAREIO1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_SPAREIO1);

SPAREIO2_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_SPAREIO2);

SPAREIO3_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_SPAREIO3);
END structure;