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123 
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V18_EM_DATA_BUF_DIR_a68);

V18_EM_DATA_BUF_DIR_a69_I : maxii_lcell
-- Equation(s):
-- V18_EM_DATA_BUF_DIR_a69 = READ_OE_acombout & ATA_DIR_acombout & (V18_EM_DATA_BUF_DIR_a68) # !READ_OE_acombout & (EM_CS2_a14 # ATA_DIR_acombout & V18_EM_DATA_BUF_DIR_a68)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "DC50",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => READ_OE_acombout,
	datab => ATA_DIR_acombout,
	datac => EM_CS2_a14,
	datad => V18_EM_DATA_BUF_DIR_a68,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V18_EM_DATA_BUF_DIR_a69);

ATA_CS1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA_CS1,
	combout => ATA_CS1_acombout);

ATA_CS0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA_CS0,
	combout => ATA_CS0_acombout);

V18_EM_DATA_BUF_EN_a192_I : maxii_lcell
-- Equation(s):
-- V18_EM_DATA_BUF_EN_a192 = !ATA_CS0_acombout # !ATA_CS1_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0FFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_CS1_acombout,
	datad => ATA_CS0_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V18_EM_DATA_BUF_EN_a192);

UART_TXD1_DMACK_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_UART_TXD1_DMACK,
	combout => UART_TXD1_DMACK_acombout);

WRITE_WE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_WRITE_WE,
	combout => WRITE_WE_acombout);

V18_EM_DATA_BUF_EN_a191_I : maxii_lcell
-- Equation(s):
-- V18_EM_DATA_BUF_EN_a191 = !ATA_SEL_acombout & (!READ_OE_acombout # !WRITE_WE_acombout # !UART_TXD1_DMACK_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "007F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => UART_TXD1_DMACK_acombout,
	datab => WRITE_WE_acombout,
	datac => READ_OE_acombout,
	datad => ATA_SEL_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V18_EM_DATA_BUF_EN_a191);

V18_EM_DATA_BUF_EN_a193_I : maxii_lcell
-- Equation(s):
-- V18_EM_DATA_BUF_EN_a193 = EM_CS2_a14 # V18_EM_DATA_BUF_EN_a191 # V18_EM_DATA_BUF_EN_a192 & V18_EM_DATA_BUF_DIR_a68

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFEA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => EM_CS2_a14,
	datab => V18_EM_DATA_BUF_EN_a192,
	datac => V18_EM_DATA_BUF_DIR_a68,
	datad => V18_EM_DATA_BUF_EN_a191,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V18_EM_DATA_BUF_EN_a193);

V33_CF_INTRQ_EM_RNW_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_CF_INTRQ_EM_RNW,
	combout => V33_CF_INTRQ_EM_RNW_acombout);

V33_ATA_INTRQ_EM_RNW_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_ATA_INTRQ_EM_RNW,
	combout => V33_ATA_INTRQ_EM_RNW_acombout);

INTRQ_EM_RNW_a2_I : maxii_lcell
-- Equation(s):
-- INTRQ_EM_RNW_a2 = ATA_SEL_acombout & (V33_CF_INTRQ_EM_RNW_acombout # !SelCF_a0) # !ATA_SEL_acombout & V33_ATA_INTRQ_EM_RNW_acombout & (V33_CF_INTRQ_EM_RNW_acombout # !SelCF_a0)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "C8FA",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => ATA_SEL_acombout,
	datab => V33_CF_INTRQ_EM_RNW_acombout,
	datac => V33_ATA_INTRQ_EM_RNW_acombout,
	datad => SelCF_a0,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => INTRQ_EM_RNW_a2);

MSP430_INT_IN_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_MSP430_INT_IN,
	combout => MSP430_INT_IN_acombout);

V33_TIMER_IN_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_TIMER_IN,
	combout => V33_TIMER_IN_acombout);

div8_a0_a_aI : maxii_lcell
-- Equation(s):
-- div8_a0_a = DFFEAS(!div8_a0_a, GLOBAL(V33_TIMER_IN_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => V33_TIMER_IN_acombout,
	datac => div8_a0_a,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => div8_a0_a);

div8_a1_a_aI : maxii_lcell
-- Equation(s):
-- div8_a1_a = DFFEAS(!div8_a1_a, GLOBAL(V33_TIMER_IN_acombout), VCC, , div8_a0_a, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00FF",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => V33_TIMER_IN_acombout,
	datad => div8_a1_a,
	aclr => GND,
	ena => div8_a0_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => div8_a1_a);

add_a38_I : maxii_lcell
-- Equation(s):
-- add_a38 = div8_a0_a & div8_a1_a

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F000",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => div8_a0_a,
	datad => div8_a1_a,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => add_a38);

div8_a2_a_aI : maxii_lcell
-- Equation(s):
-- div8_a2_a = DFFEAS(!div8_a2_a, GLOBAL(V33_TIMER_IN_acombout), VCC, , add_a38, , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F0F",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => V33_TIMER_IN_acombout,
	datac => div8_a2_a,
	aclr => GND,
	ena => add_a38,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => div8_a2_a);

ALE_EM_A1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ALE_EM_A1,
	combout => ALE_EM_A1_acombout);

V33_SM_ALE_EM_A1_a10_I : maxii_lcell
-- Equation(s):
-- V33_SM_ALE_EM_A1_a10 = !V33_SM_CEZ_acombout & ALE_EM_A1_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => V33_SM_CEZ_acombout,
	datad => ALE_EM_A1_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_SM_ALE_EM_A1_a10);

CLE_EM_A2_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_CLE_EM_A2,
	combout => CLE_EM_A2_acombout);

V33_SM_CLE_EM_A2_a10_I : maxii_lcell
-- Equation(s):
-- V33_SM_CLE_EM_A2_a10 = !V33_SM_CEZ_acombout & CLE_EM_A2_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => V33_SM_CEZ_acombout,
	datad => CLE_EM_A2_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_SM_CLE_EM_A2_a10);

V33_SM_WRITE_WE_a3_I : maxii_lcell
-- Equation(s):
-- V33_SM_WRITE_WE_a3 = V33_SM_CEZ_acombout # WRITE_WE_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => V33_SM_CEZ_acombout,
	datad => WRITE_WE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_SM_WRITE_WE_a3);

V33_SM_READ_OE_a4_I : maxii_lcell
-- Equation(s):
-- V33_SM_READ_OE_a4 = !V33_SM_CEZ_acombout & !READ_OE_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "000F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => V33_SM_CEZ_acombout,
	datad => READ_OE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_SM_READ_OE_a4);

V33_CF_WRITE_WE_a7_I : maxii_lcell
-- Equation(s):
-- V33_CF_WRITE_WE_a7 = CFN_SEL_acombout # WRITE_WE_acombout # !V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF3",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => CFN_SEL_acombout,
	datad => WRITE_WE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_WRITE_WE_a7);

V33_CF_READ_OE_a7_I : maxii_lcell
-- Equation(s):
-- V33_CF_READ_OE_a7 = CFN_SEL_acombout # READ_OE_acombout # !V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF3",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => CFN_SEL_acombout,
	datad => READ_OE_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_READ_OE_a7);

V33_CF_ATA_CS0_a7_I : maxii_lcell
-- Equation(s):
-- V33_CF_ATA_CS0_a7 = CFN_SEL_acombout # ATA_CS0_acombout # !V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF3",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => CFN_SEL_acombout,
	datad => ATA_CS0_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_ATA_CS0_a7);

V33_CF_ATA_CS1_a7_I : maxii_lcell
-- Equation(s):
-- V33_CF_ATA_CS1_a7 = CFN_SEL_acombout # ATA_CS1_acombout # !V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF3",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => CFN_SEL_acombout,
	datad => ATA_CS1_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_ATA_CS1_a7);

ATA0_EM_BA0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA0_EM_BA0,
	combout => ATA0_EM_BA0_acombout);

V33_CF_ATA0_EM_BA0_a12_I : maxii_lcell
-- Equation(s):
-- V33_CF_ATA0_EM_BA0_a12 = ATA0_EM_BA0_acombout & !CFN_SEL_acombout & V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0C00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => ATA0_EM_BA0_acombout,
	datac => CFN_SEL_acombout,
	datad => V33_CF_PWR_ON_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_ATA0_EM_BA0_a12);

ATA1_EM_BA1_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA1_EM_BA1,
	combout => ATA1_EM_BA1_acombout);

V33_CF_ATA1_EM_BA1_a12_I : maxii_lcell
-- Equation(s):
-- V33_CF_ATA1_EM_BA1_a12 = V33_CF_PWR_ON_acombout & ATA1_EM_BA1_acombout & !CFN_SEL_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00C0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => ATA1_EM_BA1_acombout,
	datad => CFN_SEL_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => V33_CF_ATA1_EM_BA1_a12);

ATA2_EM_A0_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA2_EM_A0,
	combout => ATA2_EM_A0_acombout);

V33_CF_ATA2_EM_A0_a12_I : maxii_lcell
-- Equation(s):
-- V33_CF_ATA2_EM_A0_a12 = V33_CF_PWR_ON_acombout & ATA2_EM_A0_acombout & !CFN_SEL_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "00C0",
123

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