muxcntlr.vho

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition"

-- DATE "11/10/2005 15:38:58"

-- 
-- Device: Altera EPM240GT100C3 Package TQFP100
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL output from Quartus II) only
-- 

LIBRARY IEEE, maxii;
USE IEEE.std_logic_1164.all;
USE maxii.maxii_components.all;

ENTITY 	muxcntlr IS
    PORT (
	V33_UART_RXD1 : IN std_logic;
	SPAREIO1 : IN std_logic;
	SPAREIO2 : IN std_logic;
	SPAREIO3 : IN std_logic;
	ATA_SEL : IN std_logic;
	V33_ATA_DMARQ : IN std_logic;
	V33_CF_PWR_ON : IN std_logic;
	CFN_SEL : IN std_logic;
	ATA_DIR : IN std_logic;
	V33_SM_CEZ : IN std_logic;
	EM_CS2 : IN std_logic;
	READ_OE : IN std_logic;
	WRITE_WE : IN std_logic;
	UART_TXD1_DMACK : IN std_logic;
	ATA_CS0 : IN std_logic;
	ATA_CS1 : IN std_logic;
	MSP430_INT_IN : IN std_logic;
	ALE_EM_A1 : IN std_logic;
	CLE_EM_A2 : IN std_logic;
	ATA0_EM_BA0 : IN std_logic;
	ATA1_EM_BA1 : IN std_logic;
	ATA2_EM_A0 : IN std_logic;
	V18_SYS_RESETZ : IN std_logic;
	V33_SM_WAIT_BUSY : IN std_logic;
	V33_ATA_WAIT_BUSY : IN std_logic;
	V33_CF_WAIT_BUSY : IN std_logic;
	NAND_BUSY : IN std_logic;
	V33_ATA_INTRQ_EM_RNW : IN std_logic;
	V33_CF_INTRQ_EM_RNW : IN std_logic;
	V33_TIMER_IN : IN std_logic;
	UART_RXD1_DMARQ : OUT std_logic;
	WAIT_BUSY : OUT std_logic;
	V18_EM_DATA_BUF_DIR : OUT std_logic;
	V18_EM_DATA_BUF_EN : OUT std_logic;
	INTRQ_EM_RNW : OUT std_logic;
	MSP430_INT_OUT : OUT std_logic;
	CPLD_TIMER_OUT : OUT std_logic;
	V33_SM_ALE_EM_A1 : OUT std_logic;
	V33_SM_CLE_EM_A2 : OUT std_logic;
	V33_SM_WRITE_WE : OUT std_logic;
	V33_SM_READ_OE : OUT std_logic;
	V33_SM_SM_CEZ : OUT std_logic;
	V33_CF_WRITE_WE : OUT std_logic;
	V33_CF_READ_OE : OUT std_logic;
	V33_CF_ATA_CS0 : OUT std_logic;
	V33_CF_ATA_CS1 : OUT std_logic;
	V33_CF_ATA0_EM_BA0 : OUT std_logic;
	V33_CF_ATA1_EM_BA1 : OUT std_logic;
	V33_CF_ATA2_EM_A0 : OUT std_logic;
	V33_ATA_DA0 : OUT std_logic;
	V33_ATA_DA1 : OUT std_logic;
	V33_ATA_DA2 : OUT std_logic;
	V33_ATA_DMACK : OUT std_logic;
	V33_ATA_CS0 : OUT std_logic;
	V33_ATA_CS1 : OUT std_logic;
	V33_ATA_DIOR : OUT std_logic;
	V33_ATA_DIOW : OUT std_logic;
	V33_ATA_BUFF_DIR : OUT std_logic;
	V33_ATA_BUFF_ENZ : OUT std_logic;
	V33_ATA_RESETn : OUT std_logic;
	V33_SYS_RESETZ : OUT std_logic;
	V33_UART_TXD1 : OUT std_logic
	);
END muxcntlr;

ARCHITECTURE structure OF muxcntlr IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_V33_UART_RXD1 : std_logic;
SIGNAL ww_SPAREIO1 : std_logic;
SIGNAL ww_SPAREIO2 : std_logic;
SIGNAL ww_SPAREIO3 : std_logic;
SIGNAL ww_ATA_SEL : std_logic;
SIGNAL ww_V33_ATA_DMARQ : std_logic;
SIGNAL ww_V33_CF_PWR_ON : std_logic;
SIGNAL ww_CFN_SEL : std_logic;
SIGNAL ww_ATA_DIR : std_logic;
SIGNAL ww_V33_SM_CEZ : std_logic;
SIGNAL ww_EM_CS2 : std_logic;
SIGNAL ww_READ_OE : std_logic;
SIGNAL ww_WRITE_WE : std_logic;
SIGNAL ww_UART_TXD1_DMACK : std_logic;
SIGNAL ww_ATA_CS0 : std_logic;
SIGNAL ww_ATA_CS1 : std_logic;
SIGNAL ww_MSP430_INT_IN : std_logic;
SIGNAL ww_ALE_EM_A1 : std_logic;
SIGNAL ww_CLE_EM_A2 : std_logic;
SIGNAL ww_ATA0_EM_BA0 : std_logic;
SIGNAL ww_ATA1_EM_BA1 : std_logic;
SIGNAL ww_ATA2_EM_A0 : std_logic;
SIGNAL ww_V18_SYS_RESETZ : std_logic;
SIGNAL ww_V33_SM_WAIT_BUSY : std_logic;
SIGNAL ww_V33_ATA_WAIT_BUSY : std_logic;
SIGNAL ww_V33_CF_WAIT_BUSY : std_logic;
SIGNAL ww_NAND_BUSY : std_logic;
SIGNAL ww_V33_ATA_INTRQ_EM_RNW : std_logic;
SIGNAL ww_V33_CF_INTRQ_EM_RNW : std_logic;
SIGNAL ww_V33_TIMER_IN : std_logic;
SIGNAL ww_UART_RXD1_DMARQ : std_logic;
SIGNAL ww_WAIT_BUSY : std_logic;
SIGNAL ww_V18_EM_DATA_BUF_DIR : std_logic;
SIGNAL ww_V18_EM_DATA_BUF_EN : std_logic;
SIGNAL ww_INTRQ_EM_RNW : std_logic;
SIGNAL ww_MSP430_INT_OUT : std_logic;
SIGNAL ww_CPLD_TIMER_OUT : std_logic;
SIGNAL ww_V33_SM_ALE_EM_A1 : std_logic;
SIGNAL ww_V33_SM_CLE_EM_A2 : std_logic;
SIGNAL ww_V33_SM_WRITE_WE : std_logic;
SIGNAL ww_V33_SM_READ_OE : std_logic;
SIGNAL ww_V33_SM_SM_CEZ : std_logic;
SIGNAL ww_V33_CF_WRITE_WE : std_logic;
SIGNAL ww_V33_CF_READ_OE : std_logic;
SIGNAL ww_V33_CF_ATA_CS0 : std_logic;
SIGNAL ww_V33_CF_ATA_CS1 : std_logic;
SIGNAL ww_V33_CF_ATA0_EM_BA0 : std_logic;
SIGNAL ww_V33_CF_ATA1_EM_BA1 : std_logic;
SIGNAL ww_V33_CF_ATA2_EM_A0 : std_logic;
SIGNAL ww_V33_ATA_DA0 : std_logic;
SIGNAL ww_V33_ATA_DA1 : std_logic;
SIGNAL ww_V33_ATA_DA2 : std_logic;
SIGNAL ww_V33_ATA_DMACK : std_logic;
SIGNAL ww_V33_ATA_CS0 : std_logic;
SIGNAL ww_V33_ATA_CS1 : std_logic;
SIGNAL ww_V33_ATA_DIOR : std_logic;
SIGNAL ww_V33_ATA_DIOW : std_logic;
SIGNAL ww_V33_ATA_BUFF_DIR : std_logic;
SIGNAL ww_V33_ATA_BUFF_ENZ : std_logic;
SIGNAL ww_V33_ATA_RESETn : std_logic;
SIGNAL ww_V33_SYS_RESETZ : std_logic;
SIGNAL ww_V33_UART_TXD1 : std_logic;
SIGNAL ATA_SEL_acombout : std_logic;
SIGNAL V33_ATA_DMARQ_acombout : std_logic;
SIGNAL UART_RXD1_DMARQ_a5 : std_logic;
SIGNAL V33_CF_WAIT_BUSY_acombout : std_logic;
SIGNAL NAND_BUSY_acombout : std_logic;
SIGNAL CFN_SEL_acombout : std_logic;
SIGNAL V33_CF_PWR_ON_acombout : std_logic;
SIGNAL SelCF_a0 : std_logic;
SIGNAL V33_ATA_WAIT_BUSY_acombout : std_logic;
SIGNAL V33_SM_WAIT_BUSY_acombout : std_logic;
SIGNAL V33_SM_CEZ_acombout : std_logic;
SIGNAL WAIT_BUSY_a39 : std_logic;
SIGNAL WAIT_BUSY_a5 : std_logic;
SIGNAL READ_OE_acombout : std_logic;
SIGNAL ATA_DIR_acombout : std_logic;
SIGNAL EM_CS2_acombout : std_logic;
SIGNAL EM_CS2_a14 : std_logic;
SIGNAL V18_EM_DATA_BUF_DIR_a68 : std_logic;
SIGNAL V18_EM_DATA_BUF_DIR_a69 : std_logic;
SIGNAL ATA_CS1_acombout : std_logic;
SIGNAL ATA_CS0_acombout : std_logic;
SIGNAL V18_EM_DATA_BUF_EN_a192 : std_logic;
SIGNAL UART_TXD1_DMACK_acombout : std_logic;
SIGNAL WRITE_WE_acombout : std_logic;
SIGNAL V18_EM_DATA_BUF_EN_a191 : std_logic;
SIGNAL V18_EM_DATA_BUF_EN_a193 : std_logic;
SIGNAL V33_CF_INTRQ_EM_RNW_acombout : std_logic;
SIGNAL V33_ATA_INTRQ_EM_RNW_acombout : std_logic;
SIGNAL INTRQ_EM_RNW_a2 : std_logic;
SIGNAL MSP430_INT_IN_acombout : std_logic;
SIGNAL V33_TIMER_IN_acombout : std_logic;
SIGNAL div8_a0_a : std_logic;
SIGNAL div8_a1_a : std_logic;
SIGNAL add_a38 : std_logic;
SIGNAL div8_a2_a : std_logic;
SIGNAL ALE_EM_A1_acombout : std_logic;
SIGNAL V33_SM_ALE_EM_A1_a10 : std_logic;
SIGNAL CLE_EM_A2_acombout : std_logic;
SIGNAL V33_SM_CLE_EM_A2_a10 : std_logic;
SIGNAL V33_SM_WRITE_WE_a3 : std_logic;
SIGNAL V33_SM_READ_OE_a4 : std_logic;
SIGNAL V33_CF_WRITE_WE_a7 : std_logic;
SIGNAL V33_CF_READ_OE_a7 : std_logic;
SIGNAL V33_CF_ATA_CS0_a7 : std_logic;
SIGNAL V33_CF_ATA_CS1_a7 : std_logic;
SIGNAL ATA0_EM_BA0_acombout : std_logic;
SIGNAL V33_CF_ATA0_EM_BA0_a12 : std_logic;
SIGNAL ATA1_EM_BA1_acombout : std_logic;
SIGNAL V33_CF_ATA1_EM_BA1_a12 : std_logic;
SIGNAL ATA2_EM_A0_acombout : std_logic;
SIGNAL V33_CF_ATA2_EM_A0_a12 : std_logic;
SIGNAL V33_ATA_DA0_a10 : std_logic;
SIGNAL V33_ATA_DA1_a10 : std_logic;
SIGNAL V33_ATA_DA2_a10 : std_logic;
SIGNAL V33_ATA_DMACK_a3 : std_logic;
SIGNAL V33_ATA_CS0_a3 : std_logic;
SIGNAL V33_ATA_CS1_a3 : std_logic;
SIGNAL V33_ATA_DIOR_a3 : std_logic;
SIGNAL V33_ATA_DIOW_a3 : std_logic;
SIGNAL V18_SYS_RESETZ_acombout : std_logic;
SIGNAL ALT_INV_V18_EM_DATA_BUF_EN_a193 : std_logic;
SIGNAL ALT_INV_V33_SM_READ_OE_a4 : std_logic;

BEGIN

ww_V33_UART_RXD1 <= V33_UART_RXD1;
ww_SPAREIO1 <= SPAREIO1;
ww_SPAREIO2 <= SPAREIO2;
ww_SPAREIO3 <= SPAREIO3;
ww_ATA_SEL <= ATA_SEL;
ww_V33_ATA_DMARQ <= V33_ATA_DMARQ;
ww_V33_CF_PWR_ON <= V33_CF_PWR_ON;
ww_CFN_SEL <= CFN_SEL;
ww_ATA_DIR <= ATA_DIR;
ww_V33_SM_CEZ <= V33_SM_CEZ;
ww_EM_CS2 <= EM_CS2;
ww_READ_OE <= READ_OE;
ww_WRITE_WE <= WRITE_WE;
ww_UART_TXD1_DMACK <= UART_TXD1_DMACK;
ww_ATA_CS0 <= ATA_CS0;
ww_ATA_CS1 <= ATA_CS1;
ww_MSP430_INT_IN <= MSP430_INT_IN;
ww_ALE_EM_A1 <= ALE_EM_A1;
ww_CLE_EM_A2 <= CLE_EM_A2;
ww_ATA0_EM_BA0 <= ATA0_EM_BA0;
ww_ATA1_EM_BA1 <= ATA1_EM_BA1;
ww_ATA2_EM_A0 <= ATA2_EM_A0;
ww_V18_SYS_RESETZ <= V18_SYS_RESETZ;
ww_V33_SM_WAIT_BUSY <= V33_SM_WAIT_BUSY;
ww_V33_ATA_WAIT_BUSY <= V33_ATA_WAIT_BUSY;
ww_V33_CF_WAIT_BUSY <= V33_CF_WAIT_BUSY;
ww_NAND_BUSY <= NAND_BUSY;
ww_V33_ATA_INTRQ_EM_RNW <= V33_ATA_INTRQ_EM_RNW;
ww_V33_CF_INTRQ_EM_RNW <= V33_CF_INTRQ_EM_RNW;
ww_V33_TIMER_IN <= V33_TIMER_IN;
UART_RXD1_DMARQ <= ww_UART_RXD1_DMARQ;
WAIT_BUSY <= ww_WAIT_BUSY;
V18_EM_DATA_BUF_DIR <= ww_V18_EM_DATA_BUF_DIR;
V18_EM_DATA_BUF_EN <= ww_V18_EM_DATA_BUF_EN;
INTRQ_EM_RNW <= ww_INTRQ_EM_RNW;
MSP430_INT_OUT <= ww_MSP430_INT_OUT;
CPLD_TIMER_OUT <= ww_CPLD_TIMER_OUT;
V33_SM_ALE_EM_A1 <= ww_V33_SM_ALE_EM_A1;
V33_SM_CLE_EM_A2 <= ww_V33_SM_CLE_EM_A2;
V33_SM_WRITE_WE <= ww_V33_SM_WRITE_WE;
V33_SM_READ_OE <= ww_V33_SM_READ_OE;
V33_SM_SM_CEZ <= ww_V33_SM_SM_CEZ;
V33_CF_WRITE_WE <= ww_V33_CF_WRITE_WE;
V33_CF_READ_OE <= ww_V33_CF_READ_OE;
V33_CF_ATA_CS0 <= ww_V33_CF_ATA_CS0;
V33_CF_ATA_CS1 <= ww_V33_CF_ATA_CS1;
V33_CF_ATA0_EM_BA0 <= ww_V33_CF_ATA0_EM_BA0;
V33_CF_ATA1_EM_BA1 <= ww_V33_CF_ATA1_EM_BA1;
V33_CF_ATA2_EM_A0 <= ww_V33_CF_ATA2_EM_A0;
V33_ATA_DA0 <= ww_V33_ATA_DA0;
V33_ATA_DA1 <= ww_V33_ATA_DA1;
V33_ATA_DA2 <= ww_V33_ATA_DA2;
V33_ATA_DMACK <= ww_V33_ATA_DMACK;
V33_ATA_CS0 <= ww_V33_ATA_CS0;
V33_ATA_CS1 <= ww_V33_ATA_CS1;
V33_ATA_DIOR <= ww_V33_ATA_DIOR;
V33_ATA_DIOW <= ww_V33_ATA_DIOW;
V33_ATA_BUFF_DIR <= ww_V33_ATA_BUFF_DIR;
V33_ATA_BUFF_ENZ <= ww_V33_ATA_BUFF_ENZ;
V33_ATA_RESETn <= ww_V33_ATA_RESETn;
V33_SYS_RESETZ <= ww_V33_SYS_RESETZ;
V33_UART_TXD1 <= ww_V33_UART_TXD1;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
ALT_INV_V18_EM_DATA_BUF_EN_a193 <= NOT V18_EM_DATA_BUF_EN_a193;
ALT_INV_V33_SM_READ_OE_a4 <= NOT V33_SM_READ_OE_a4;

ATA_SEL_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA_SEL,
	combout => ATA_SEL_acombout);

V33_ATA_DMARQ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_ATA_DMARQ,
	combout => V33_ATA_DMARQ_acombout);

UART_RXD1_DMARQ_a5_I : maxii_lcell
-- Equation(s):
-- UART_RXD1_DMARQ_a5 = ATA_SEL_acombout # V33_ATA_DMARQ_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FFF0",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => ATA_SEL_acombout,
	datad => V33_ATA_DMARQ_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => UART_RXD1_DMARQ_a5);

V33_CF_WAIT_BUSY_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_CF_WAIT_BUSY,
	combout => V33_CF_WAIT_BUSY_acombout);

NAND_BUSY_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_NAND_BUSY,
	combout => NAND_BUSY_acombout);

CFN_SEL_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_CFN_SEL,
	combout => CFN_SEL_acombout);

V33_CF_PWR_ON_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_CF_PWR_ON,
	combout => V33_CF_PWR_ON_acombout);

SelCF_a0_I : maxii_lcell
-- Equation(s):
-- SelCF_a0 = !CFN_SEL_acombout & V33_CF_PWR_ON_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0F00",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => CFN_SEL_acombout,
	datad => V33_CF_PWR_ON_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => SelCF_a0);

V33_ATA_WAIT_BUSY_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_ATA_WAIT_BUSY,
	combout => V33_ATA_WAIT_BUSY_acombout);

V33_SM_WAIT_BUSY_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_SM_WAIT_BUSY,
	combout => V33_SM_WAIT_BUSY_acombout);

V33_SM_CEZ_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_V33_SM_CEZ,
	combout => V33_SM_CEZ_acombout);

WAIT_BUSY_a39_I : maxii_lcell
-- Equation(s):
-- WAIT_BUSY_a39 = ATA_SEL_acombout & (!V33_SM_WAIT_BUSY_acombout & !V33_SM_CEZ_acombout) # !ATA_SEL_acombout & (!V33_SM_WAIT_BUSY_acombout & !V33_SM_CEZ_acombout # !V33_ATA_WAIT_BUSY_acombout)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "111F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => ATA_SEL_acombout,
	datab => V33_ATA_WAIT_BUSY_acombout,
	datac => V33_SM_WAIT_BUSY_acombout,
	datad => V33_SM_CEZ_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => WAIT_BUSY_a39);

WAIT_BUSY_a5_I : maxii_lcell
-- Equation(s):
-- WAIT_BUSY_a5 = NAND_BUSY_acombout & !WAIT_BUSY_a39 & (V33_CF_WAIT_BUSY_acombout # !SelCF_a0)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "008C",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	dataa => V33_CF_WAIT_BUSY_acombout,
	datab => NAND_BUSY_acombout,
	datac => SelCF_a0,
	datad => WAIT_BUSY_a39,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => WAIT_BUSY_a5);

READ_OE_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_READ_OE,
	combout => READ_OE_acombout);

ATA_DIR_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_ATA_DIR,
	combout => ATA_DIR_acombout);

EM_CS2_aI : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_EM_CS2,
	combout => EM_CS2_acombout);

EM_CS2_a14_I : maxii_lcell
-- Equation(s):
-- EM_CS2_a14 = !EM_CS2_acombout & !V33_SM_CEZ_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "000F",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => EM_CS2_acombout,
	datad => V33_SM_CEZ_acombout,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => EM_CS2_a14);

V18_EM_DATA_BUF_DIR_a68_I : maxii_lcell
-- Equation(s):
-- V18_EM_DATA_BUF_DIR_a68 = V33_CF_PWR_ON_acombout & !CFN_SEL_acombout # !ATA_SEL_acombout

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0CFF",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => V33_CF_PWR_ON_acombout,
	datac => CFN_SEL_acombout,
	datad => ATA_SEL_acombout,