muxcntlr.qsf

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# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		muxcntlr_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:11:12  SEPTEMBER 30, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name VHDL_FILE muxcntlr.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_2 -to V18_EM_DATA_BUF_DIR
set_location_assignment PIN_27 -to UART_RXD1_DMARQ
set_location_assignment PIN_3 -to V18_EM_DATA_BUF_EN
set_location_assignment PIN_42 -to WAIT_BUSY
set_location_assignment PIN_38 -to INTRQ_EM_RNW
set_location_assignment PIN_5 -to CLE_EM_A2
set_location_assignment PIN_6 -to ALE_EM_A1
set_location_assignment PIN_7 -to ATA2_EM_A0
set_location_assignment PIN_8 -to ATA1_EM_BA1
set_location_assignment PIN_34 -to ATA0_EM_BA0
set_location_assignment PIN_16 -to WRITE_WE
set_location_assignment PIN_17 -to READ_OE
set_location_assignment PIN_30 -to ATA_DIR
set_location_assignment PIN_20 -to ATA_CS1
set_location_assignment PIN_21 -to ATA_CS0
set_location_assignment PIN_26 -to UART_TXD1_DMACK
set_location_assignment PIN_19 -to EM_CS2
set_location_assignment PIN_51 -to V18_SYS_RESETZ
set_location_assignment PIN_55 -to CFN_SEL
set_location_assignment PIN_54 -to ATA_SEL
set_location_assignment PIN_52 -to MSP430_INT_IN
set_location_assignment PIN_92 -to V33_SM_ALE_EM_A1
set_location_assignment PIN_95 -to V33_SM_CLE_EM_A2
set_location_assignment PIN_96 -to V33_SM_WRITE_WE
set_location_assignment PIN_97 -to V33_SM_READ_OE
set_location_assignment PIN_85 -to V33_CF_WRITE_WE
set_location_assignment PIN_86 -to V33_CF_READ_OE
set_location_assignment PIN_87 -to V33_CF_ATA_CS0
set_location_assignment PIN_88 -to V33_CF_ATA_CS1
set_location_assignment PIN_89 -to V33_CF_ATA0_EM_BA0
set_location_assignment PIN_90 -to V33_CF_ATA1_EM_BA1
set_location_assignment PIN_91 -to V33_CF_ATA2_EM_A0
set_location_assignment PIN_70 -to V33_ATA_DA0
set_location_assignment PIN_69 -to V33_ATA_DA1
set_location_assignment PIN_67 -to V33_ATA_DA2
set_location_assignment PIN_68 -to V33_ATA_DMACK
set_location_assignment PIN_61 -to V33_ATA_CS0
set_location_assignment PIN_66 -to V33_ATA_CS1
set_location_assignment PIN_71 -to V33_ATA_DIOR
set_location_assignment PIN_72 -to V33_ATA_DIOW
set_location_assignment PIN_73 -to V33_ATA_RESETn
set_location_assignment PIN_78 -to V33_UART_TXD1
set_location_assignment PIN_98 -to V33_SM_SM_CEZ
set_location_assignment PIN_99 -to V33_SM_WAIT_BUSY
set_location_assignment PIN_83 -to V33_CF_INTRQ_EM_RNW
set_location_assignment PIN_84 -to V33_CF_WAIT_BUSY
set_location_assignment PIN_56 -to V33_ATA_DMARQ
set_location_assignment PIN_57 -to V33_ATA_INTRQ_EM_RNW
set_location_assignment PIN_58 -to V33_ATA_WAIT_BUSY
set_location_assignment PIN_74 -to V33_ATA_BUFF_DIR
set_location_assignment PIN_75 -to V33_ATA_BUFF_ENZ
set_location_assignment PIN_53 -to V33_SYS_RESETZ
set_location_assignment PIN_77 -to V33_UART_RXD1
set_location_assignment PIN_1 -to V33_SM_CEZ
set_location_assignment PIN_39 -to MSP430_INT_OUT
set_location_assignment PIN_100 -to V33_CF_PWR_ON
set_location_assignment PIN_82 -to SPAREIO1
set_location_assignment PIN_81 -to SPAREIO2
set_location_assignment PIN_76 -to SPAREIO3
set_location_assignment PIN_4 -to NAND_BUSY
set_location_assignment PIN_37 -to CPLD_TIMER_OUT
set_location_assignment PIN_62 -to V33_TIMER_IN

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY muxcntlr

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EPM240GT100C3
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_instance_assignment -name IO_STANDARD "1.8 V" -to ALE_EM_A1
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA0_EM_BA0
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA1_EM_BA1
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA2_EM_A0
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA_CS0
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA_CS1
set_instance_assignment -name IO_STANDARD "1.8 V" -to ATA_DIR
set_instance_assignment -name IO_STANDARD "1.8 V" -to CLE_EM_A2
set_instance_assignment -name IO_STANDARD "1.8 V" -to EM_CS2
set_instance_assignment -name IO_STANDARD "1.8 V" -to INTRQ_EM_RNW
set_instance_assignment -name IO_STANDARD "1.8 V" -to MSP430_INT_OUT
set_instance_assignment -name IO_STANDARD "1.8 V" -to READ_OE
set_instance_assignment -name IO_STANDARD "1.8 V" -to UART_RXD1_DMARQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to UART_TXD1_DMACK
set_instance_assignment -name IO_STANDARD "1.8 V" -to V18_EM_DATA_BUF_DIR
set_instance_assignment -name IO_STANDARD "1.8 V" -to V18_EM_DATA_BUF_EN
set_instance_assignment -name IO_STANDARD "1.8 V" -to V18_SYS_RESETZ
set_instance_assignment -name IO_STANDARD "1.8 V" -to WAIT_BUSY
set_instance_assignment -name IO_STANDARD "1.8 V" -to WRITE_WE
set_instance_assignment -name IO_STANDARD LVTTL -to V33_UART_RXD1
set_instance_assignment -name IO_STANDARD "1.8 V" -to NAND_BUSY
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_TIMER_OUT

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL output from Quartus II)"

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
	set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES ON -section_id eda_design_synthesis
	set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------