📄 muxcntlr.fit.rpt
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+----------------------------+-------------------+
; C4s ; 41 / 784 ( 5 % ) ;
; Direct links ; 4 / 888 ( < 1 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 2 / 32 ( 6 % ) ;
; LUT chains ; 1 / 216 ( < 1 % ) ;
; Local interconnects ; 68 / 888 ( 7 % ) ;
; R4s ; 40 / 704 ( 5 % ) ;
+----------------------------+-------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 3.09) ; Number of LABs (Total = 11) ;
+--------------------------------------------+------------------------------+
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 3 ;
; 4 ; 0 ;
; 5 ; 4 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 0.27) ; Number of LABs (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Clock ; 2 ;
; 1 Clock enable ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 3.09) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 3 ;
; 4 ; 0 ;
; 5 ; 4 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 2.64) ; Number of LABs (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 3 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 5.36) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Nov 10 15:38:51 2005
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr
Info: Selected device EPM240GT100C3 for design "muxcntlr"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570GT100C3 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "V33_TIMER_IN" to use Global clock in PIN 62
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is pin to pin delay of 6.469 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_54; Fanout = 14; PIN Node = 'ATA_SEL'
Info: 2: + IC(2.214 ns) + CELL(0.125 ns) = 3.047 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_EN~191'
Info: 3: + IC(0.277 ns) + CELL(0.462 ns) = 3.786 ns; Loc. = LAB_X2_Y4; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_EN~193'
Info: 4: + IC(0.371 ns) + CELL(2.312 ns) = 6.469 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_EN'
Info: Total cell delay = 3.607 ns ( 55.76 % )
Info: Total interconnect delay = 2.862 ns ( 44.24 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Nov 10 15:38:52 2005
Info: Elapsed time: 00:00:02
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