muxcntlr_orig.vhd

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------------------------------------------------------------------------------------
-- $Archive::                                                                      $
-- $Revision::                                                                     $
-- $Date::                                                                         $
-- $Author::                                                                       $
--
--
-- Copyright ( c ) 2005, Spectrum Digital Incorporated
-- All rights reserved
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
-- Start the real code
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity muxcntlr is
  port
  (
    -- Bank1
    CLE_EM_A2                   : in  std_logic;
    ALE_EM_A1                   : in  std_logic;
    ATA2_EM_A0                  : in  std_logic;
    ATA1_EM_BA1                 : in  std_logic;
    ATA0_EM_BA0                 : in  std_logic;
    WRITE_WE                    : in  std_logic;
    READ_OE                     : in  std_logic;
    ATA_DIR                     : in  std_logic;
    ATA_CS1                     : in  std_logic;
    ATA_CS0                     : in  std_logic;

    UART_TXD1_DMACK             : in  std_logic;
    UART_RXD1_DMARQ             : out std_logic;
    EM_CS2                      : in  std_logic;
    WAIT_BUSY                   : out std_logic;
    V18_EM_DATA_BUF_DIR         : out std_logic;
    V18_EM_DATA_BUF_EN          : out std_logic;
    V18_SYS_RESETZ              : in  std_logic;

    INTRQ_EM_RNW                : out std_logic;
    MSP430_INT_OUT              : out std_logic;

    -- Bank2
    V33_SM_ALE_EM_A1            : out std_logic;
    V33_SM_CLE_EM_A2            : out std_logic;
    V33_SM_WRITE_WE             : out std_logic;
    V33_SM_READ_OE              : out std_logic;
    V33_SM_SM_CEZ               : out std_logic;

    V33_SM_WAIT_BUSY            : in  std_logic;

    V33_CF_INTRQ_EM_RNW         : in  std_logic;
    V33_CF_WAIT_BUSY            : in  std_logic;
    V33_CF_WRITE_WE             : out std_logic;
    V33_CF_READ_OE              : out std_logic;
    V33_CF_ATA_CS0              : out std_logic;
    V33_CF_ATA_CS1              : out std_logic;
    V33_CF_ATA0_EM_BA0          : out std_logic;
    V33_CF_ATA1_EM_BA1          : out std_logic;
    V33_CF_ATA2_EM_A0           : out std_logic;

    V33_ATA_DMARQ               : in  std_logic;
    V33_ATA_INTRQ_EM_RNW        : in  std_logic;
    V33_ATA_WAIT_BUSY           : in  std_logic;
    V33_ATA_DA0                 : out std_logic;
    V33_ATA_DA1                 : out std_logic;
    V33_ATA_DA2                 : out std_logic;
    V33_ATA_DMACK               : out std_logic;
    V33_ATA_CS0                 : out std_logic;
    V33_ATA_CS1                 : out std_logic;
    V33_ATA_DIOR                : out std_logic;
    V33_ATA_DIOW                : out std_logic;
    V33_ATA_BUFF_DIR            : out std_logic;
    V33_ATA_BUFF_ENZ            : out std_logic;
    V33_ATA_RESETn              : out std_logic;

    V33_SYS_RESETZ              : out std_logic;
    V33_UART_RXD1               : in  std_logic;
    V33_UART_TXD1               : out std_logic;

    V33_SM_CEZ                  : in  std_logic;
    CFN_SEL                     : in  std_logic;
    ATA_SEL                     : in  std_logic;

    MSP430_INT_IN               : in  std_logic;
    V33_CF_PWR_ON               : in  std_logic
 );
end muxcntlr;

-----------------------------------------------------------------------------------
-- Include standard librariess
-----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- use work.std_arith.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

architecture behavior_muxcntlr of muxcntlr is

-----------------------------------------------------------------------------------
-- Add local components in here
-----------------------------------------------------------------------------------

-----------------------------------------------------------------------------------
-- Add signals
-----------------------------------------------------------------------------------
    signal  SelSM       : std_logic;
    signal  SelCF       : std_logic;
    signal  SelATA      : std_logic;

    signal  DefaultSM   : std_logic;
    signal  DefaultCF   : std_logic;
    signal  DefaultATA  : std_logic;

-----------------------------------------------------------------------------------
-- The implementation
-----------------------------------------------------------------------------------

begin
-----------------------------------------------------------------------------------
-- Map the other components
-----------------------------------------------------------------------------------

    DefaultSM           <= '1';
    DefaultCF           <= '1';
    DefaultATA          <= '1';

    SelSM               <= '1' when V33_SM_CEZ = '0' else '0';
    SelCF               <= '1' when CFN_SEL    = '0' and V33_CF_PWR_ON ='1' else '0';
    SelATA              <= '1' when ATA_SEL    = '0' else '0';

    ---------------------------------------------------------------------------------
    -- BEGIN:SM
    V33_SM_ALE_EM_A1    <= ALE_EM_A1        when SelSM = '1' else DefaultSM;
    V33_SM_CLE_EM_A2    <= CLE_EM_A2        when SelSM = '1' else DefaultSM;
    V33_SM_WRITE_WE     <= WRITE_WE         when SelSM = '1' else DefaultSM;
    V33_SM_READ_OE      <= READ_OE          when SelSM = '1' else DefaultSM;
    V33_SM_SM_CEZ       <= SelSM;

    ---------------------------------------------------------------------------------
    -- BEGIN: CF
    V33_CF_WRITE_WE     <= WRITE_WE         when SelCF = '1' else DefaultCF;
    V33_CF_READ_OE      <= READ_OE          when SelCF = '1' else DefaultCF;
    V33_CF_ATA_CS0      <= ATA_CS0          when SelCF = '1' else DefaultCF;
    V33_CF_ATA_CS1      <= ATA_CS1          when SelCF = '1' else DefaultCF;
    V33_CF_ATA0_EM_BA0  <= ATA0_EM_BA0      when SelCF = '1' else DefaultCF;
    V33_CF_ATA1_EM_BA1  <= ATA1_EM_BA1      when SelCF = '1' else DefaultCF;
    V33_CF_ATA2_EM_A0   <= ATA2_EM_A0       when SelCF = '1' else DefaultCF;

    ---------------------------------------------------------------------------------
    -- BEGIN: ATA
    V33_ATA_DA0         <= ATA2_EM_A0       when SelATA = '1' else DefaultATA;
    V33_ATA_DA1         <= ALE_EM_A1        when SelATA = '1' else DefaultATA;
    V33_ATA_DA2         <= CLE_EM_A2        when SelATA = '1' else DefaultATA;
    V33_ATA_DMACK       <= UART_TXD1_DMACK  when SelATA = '1' else DefaultATA;
    V33_ATA_CS0         <= ATA_CS0          when SelATA = '1' else DefaultATA;
    V33_ATA_CS1         <= ATA_CS1          when SelATA = '1' else DefaultATA;
    V33_ATA_DIOR        <= READ_OE          when SelATA = '1' else DefaultATA;
    V33_ATA_DIOW        <= WRITE_WE         when SelATA = '1' else DefaultATA;
    V33_ATA_RESETn      <= V18_SYS_RESETZ   when SelATA = '1' else DefaultATA;

    V33_ATA_BUFF_DIR    <= ATA_DIR;
    V33_ATA_BUFF_ENZ    <= '0'              when SelATA = '1' else '1';

    ---------------------------------------------------------------------------------
    -- BEGIN: MISC
    V33_SYS_RESETZ      <= V18_SYS_RESETZ;
    V33_UART_TXD1       <= UART_TXD1_DMACK  when SelATA = '0' else '1';

    UART_RXD1_DMARQ     <= V33_UART_RXD1    when SelATA = '0' else V33_ATA_DMARQ;

    V18_EM_DATA_BUF_DIR <= '0'              when ( SelATA = '1' and ATA_DIR = '0' )
                                              or ( SelCF  = '1' and ATA_DIR = '0' )
                                              or ( SelSM  = '1' and EM_CS2  = '0' and WRITE_WE = '0' )
                                            else '1';

    V18_EM_DATA_BUF_EN  <= '0'              when SelSM = '1' or SelCF = '1' or SelATA = '1' else '1';

    WAIT_BUSY           <= '0'              when ( SelATA = '1' and V33_ATA_WAIT_BUSY = '0' )
                                              or ( SelCF  = '1' and V33_CF_WAIT_BUSY  = '0' )
                                              or ( SelSM  = '1' and V33_SM_WAIT_BUSY  = '0' )
                                            else 'Z';

    INTRQ_EM_RNW        <= '0'              when ( SelATA = '1' and V33_ATA_INTRQ_EM_RNW = '0' )
                                              or ( SelCF  = '1' and V33_CF_INTRQ_EM_RNW  = '0' )
                                            else 'Z';


    MSP430_INT_OUT <= MSP430_INT_IN;
-----------------------------------------------------------------------------------
-- Now define the logic
-----------------------------------------------------------------------------------

end behavior_muxcntlr;