muxcntlr.map.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L03 is UART_RXD1_DMARQ~5
--operation mode is normal

A1L03 = ATA_SEL # V33_ATA_DMARQ;


--A1L33 is V18_EM_DATA_BUF_DIR~68
--operation mode is normal

A1L33 = V33_CF_PWR_ON & !CFN_SEL # !ATA_SEL;


--A1L81 is EM_CS2~14
--operation mode is normal

A1L81 = !V33_SM_CEZ & !EM_CS2;


--A1L43 is V18_EM_DATA_BUF_DIR~69
--operation mode is normal

A1L43 = A1L33 & (ATA_DIR # A1L81 & !READ_OE) # !A1L33 & (A1L81 & !READ_OE);


--A1L63 is V18_EM_DATA_BUF_EN~191
--operation mode is normal

A1L63 = !ATA_SEL & (!UART_TXD1_DMACK # !WRITE_WE # !READ_OE);


--A1L73 is V18_EM_DATA_BUF_EN~192
--operation mode is normal

A1L73 = !ATA_CS1 # !ATA_CS0;


--A1L83 is V18_EM_DATA_BUF_EN~193
--operation mode is normal

A1L83 = A1L81 # A1L63 # A1L33 & A1L73;


--div8[2] is div8[2]
--operation mode is normal

div8[2]_lut_out = !div8[2];
div8[2] = DFFEAS(div8[2]_lut_out, V33_TIMER_IN, VCC, , A1L1, , , , );


--A1L08 is V33_SM_ALE_EM_A1~10
--operation mode is normal

A1L08 = ALE_EM_A1 & (!V33_SM_CEZ);


--A1L38 is V33_SM_CLE_EM_A2~10
--operation mode is normal

A1L38 = CLE_EM_A2 & (!V33_SM_CEZ);


--A1L98 is V33_SM_WRITE_WE~3
--operation mode is normal

A1L98 = V33_SM_CEZ # WRITE_WE;


--A1L58 is V33_SM_READ_OE~4
--operation mode is normal

A1L58 = !READ_OE & !V33_SM_CEZ;


--A1L87 is V33_CF_WRITE_WE~7
--operation mode is normal

A1L87 = CFN_SEL # WRITE_WE # !V33_CF_PWR_ON;


--A1L57 is V33_CF_READ_OE~7
--operation mode is normal

A1L57 = READ_OE # CFN_SEL # !V33_CF_PWR_ON;


--A1L96 is V33_CF_ATA_CS0~7
--operation mode is normal

A1L96 = CFN_SEL # ATA_CS0 # !V33_CF_PWR_ON;


--A1L17 is V33_CF_ATA_CS1~7
--operation mode is normal

A1L17 = CFN_SEL # ATA_CS1 # !V33_CF_PWR_ON;


--A1L36 is V33_CF_ATA0_EM_BA0~12
--operation mode is normal

A1L36 = V33_CF_PWR_ON & ATA0_EM_BA0 & (!CFN_SEL);


--A1L56 is V33_CF_ATA1_EM_BA1~12
--operation mode is normal

A1L56 = V33_CF_PWR_ON & ATA1_EM_BA1 & (!CFN_SEL);


--A1L76 is V33_CF_ATA2_EM_A0~12
--operation mode is normal

A1L76 = V33_CF_PWR_ON & ATA2_EM_A0 & (!CFN_SEL);


--A1L74 is V33_ATA_DA0~10
--operation mode is normal

A1L74 = ATA0_EM_BA0 & (!ATA_SEL);


--A1L94 is V33_ATA_DA1~10
--operation mode is normal

A1L94 = ATA1_EM_BA1 & (!ATA_SEL);


--A1L15 is V33_ATA_DA2~10
--operation mode is normal

A1L15 = ATA2_EM_A0 & (!ATA_SEL);


--A1L75 is V33_ATA_DMACK~3
--operation mode is normal

A1L75 = ATA_SEL # UART_TXD1_DMACK;


--A1L34 is V33_ATA_CS0~3
--operation mode is normal

A1L34 = ATA_SEL # ATA_CS0;


--A1L54 is V33_ATA_CS1~3
--operation mode is normal

A1L54 = ATA_SEL # ATA_CS1;


--A1L35 is V33_ATA_DIOR~3
--operation mode is normal

A1L35 = ATA_SEL # READ_OE;


--A1L55 is V33_ATA_DIOW~3
--operation mode is normal

A1L55 = ATA_SEL # WRITE_WE;


--A1L69 is WAIT_BUSY~39
--operation mode is normal

A1L69 = ATA_SEL & !V33_SM_CEZ & !V33_SM_WAIT_BUSY # !ATA_SEL & (!V33_SM_CEZ & !V33_SM_WAIT_BUSY # !V33_ATA_WAIT_BUSY);


--A1L52 is SelCF~0
--operation mode is normal

A1L52 = V33_CF_PWR_ON & (!CFN_SEL);


--A1L59 is WAIT_BUSY~5
--operation mode is normal

A1L59 = !A1L69 & NAND_BUSY & (V33_CF_WAIT_BUSY # !A1L52);


--A1L02 is INTRQ_EM_RNW~2
--operation mode is normal

A1L02 = A1L52 & V33_CF_INTRQ_EM_RNW & (ATA_SEL # V33_ATA_INTRQ_EM_RNW) # !A1L52 & (ATA_SEL # V33_ATA_INTRQ_EM_RNW);


--div8[1] is div8[1]
--operation mode is normal

div8[1]_lut_out = !div8[1];
div8[1] = DFFEAS(div8[1]_lut_out, V33_TIMER_IN, VCC, , div8[0], , , , );


--div8[0] is div8[0]
--operation mode is normal

div8[0]_lut_out = !div8[0];
div8[0] = DFFEAS(div8[0]_lut_out, V33_TIMER_IN, VCC, , , , , , );


--A1L1 is add~38
--operation mode is normal

A1L1 = div8[1] & div8[0];


--V33_UART_RXD1 is V33_UART_RXD1
--operation mode is input

V33_UART_RXD1 = INPUT();


--SPAREIO1 is SPAREIO1
--operation mode is input

SPAREIO1 = INPUT();


--SPAREIO2 is SPAREIO2
--operation mode is input

SPAREIO2 = INPUT();


--SPAREIO3 is SPAREIO3
--operation mode is input

SPAREIO3 = INPUT();


--ATA_SEL is ATA_SEL
--operation mode is input

ATA_SEL = INPUT();


--V33_ATA_DMARQ is V33_ATA_DMARQ
--operation mode is input

V33_ATA_DMARQ = INPUT();


--V33_CF_PWR_ON is V33_CF_PWR_ON
--operation mode is input

V33_CF_PWR_ON = INPUT();


--CFN_SEL is CFN_SEL
--operation mode is input

CFN_SEL = INPUT();


--ATA_DIR is ATA_DIR
--operation mode is input

ATA_DIR = INPUT();


--V33_SM_CEZ is V33_SM_CEZ
--operation mode is input

V33_SM_CEZ = INPUT();


--EM_CS2 is EM_CS2
--operation mode is input

EM_CS2 = INPUT();


--READ_OE is READ_OE
--operation mode is input

READ_OE = INPUT();


--WRITE_WE is WRITE_WE
--operation mode is input

WRITE_WE = INPUT();


--UART_TXD1_DMACK is UART_TXD1_DMACK
--operation mode is input

UART_TXD1_DMACK = INPUT();


--ATA_CS0 is ATA_CS0
--operation mode is input

ATA_CS0 = INPUT();


--ATA_CS1 is ATA_CS1
--operation mode is input

ATA_CS1 = INPUT();


--MSP430_INT_IN is MSP430_INT_IN
--operation mode is input

MSP430_INT_IN = INPUT();


--ALE_EM_A1 is ALE_EM_A1
--operation mode is input

ALE_EM_A1 = INPUT();


--CLE_EM_A2 is CLE_EM_A2
--operation mode is input

CLE_EM_A2 = INPUT();


--ATA0_EM_BA0 is ATA0_EM_BA0
--operation mode is input

ATA0_EM_BA0 = INPUT();


--ATA1_EM_BA1 is ATA1_EM_BA1
--operation mode is input

ATA1_EM_BA1 = INPUT();


--ATA2_EM_A0 is ATA2_EM_A0
--operation mode is input

ATA2_EM_A0 = INPUT();


--V18_SYS_RESETZ is V18_SYS_RESETZ
--operation mode is input

V18_SYS_RESETZ = INPUT();


--V33_SM_WAIT_BUSY is V33_SM_WAIT_BUSY
--operation mode is input

V33_SM_WAIT_BUSY = INPUT();


--V33_ATA_WAIT_BUSY is V33_ATA_WAIT_BUSY
--operation mode is input

V33_ATA_WAIT_BUSY = INPUT();


--V33_CF_WAIT_BUSY is V33_CF_WAIT_BUSY
--operation mode is input

V33_CF_WAIT_BUSY = INPUT();


--NAND_BUSY is NAND_BUSY
--operation mode is input

NAND_BUSY = INPUT();


--V33_ATA_INTRQ_EM_RNW is V33_ATA_INTRQ_EM_RNW
--operation mode is input

V33_ATA_INTRQ_EM_RNW = INPUT();


--V33_CF_INTRQ_EM_RNW is V33_CF_INTRQ_EM_RNW
--operation mode is input

V33_CF_INTRQ_EM_RNW = INPUT();


--V33_TIMER_IN is V33_TIMER_IN
--operation mode is input

V33_TIMER_IN = INPUT();


--UART_RXD1_DMARQ is UART_RXD1_DMARQ
--operation mode is output

UART_RXD1_DMARQ = OUTPUT(A1L03);


--WAIT_BUSY is WAIT_BUSY
--operation mode is output

WAIT_BUSY = OUTPUT(OPNDRN(A1L59));


--V18_EM_DATA_BUF_DIR is V18_EM_DATA_BUF_DIR
--operation mode is output

V18_EM_DATA_BUF_DIR = OUTPUT(A1L43);


--V18_EM_DATA_BUF_EN is V18_EM_DATA_BUF_EN
--operation mode is output

V18_EM_DATA_BUF_EN = OUTPUT(!A1L83);


--INTRQ_EM_RNW is INTRQ_EM_RNW
--operation mode is output

INTRQ_EM_RNW = OUTPUT(OPNDRN(A1L02));


--MSP430_INT_OUT is MSP430_INT_OUT
--operation mode is output

MSP430_INT_OUT = OUTPUT(MSP430_INT_IN);


--CPLD_TIMER_OUT is CPLD_TIMER_OUT
--operation mode is output

CPLD_TIMER_OUT = OUTPUT(div8[2]);


--V33_SM_ALE_EM_A1 is V33_SM_ALE_EM_A1
--operation mode is output

V33_SM_ALE_EM_A1 = OUTPUT(A1L08);


--V33_SM_CLE_EM_A2 is V33_SM_CLE_EM_A2
--operation mode is output

V33_SM_CLE_EM_A2 = OUTPUT(A1L38);


--V33_SM_WRITE_WE is V33_SM_WRITE_WE
--operation mode is output

V33_SM_WRITE_WE = OUTPUT(A1L98);


--V33_SM_READ_OE is V33_SM_READ_OE
--operation mode is output

V33_SM_READ_OE = OUTPUT(!A1L58);


--V33_SM_SM_CEZ is V33_SM_SM_CEZ
--operation mode is output

V33_SM_SM_CEZ = OUTPUT(V33_SM_CEZ);


--V33_CF_WRITE_WE is V33_CF_WRITE_WE
--operation mode is output

V33_CF_WRITE_WE = OUTPUT(A1L87);


--V33_CF_READ_OE is V33_CF_READ_OE
--operation mode is output

V33_CF_READ_OE = OUTPUT(A1L57);


--V33_CF_ATA_CS0 is V33_CF_ATA_CS0
--operation mode is output

V33_CF_ATA_CS0 = OUTPUT(A1L96);


--V33_CF_ATA_CS1 is V33_CF_ATA_CS1
--operation mode is output

V33_CF_ATA_CS1 = OUTPUT(A1L17);


--V33_CF_ATA0_EM_BA0 is V33_CF_ATA0_EM_BA0
--operation mode is output

V33_CF_ATA0_EM_BA0 = OUTPUT(A1L36);


--V33_CF_ATA1_EM_BA1 is V33_CF_ATA1_EM_BA1
--operation mode is output

V33_CF_ATA1_EM_BA1 = OUTPUT(A1L56);


--V33_CF_ATA2_EM_A0 is V33_CF_ATA2_EM_A0
--operation mode is output

V33_CF_ATA2_EM_A0 = OUTPUT(A1L76);


--V33_ATA_DA0 is V33_ATA_DA0
--operation mode is output

V33_ATA_DA0 = OUTPUT(A1L74);


--V33_ATA_DA1 is V33_ATA_DA1
--operation mode is output

V33_ATA_DA1 = OUTPUT(A1L94);


--V33_ATA_DA2 is V33_ATA_DA2
--operation mode is output

V33_ATA_DA2 = OUTPUT(A1L15);


--V33_ATA_DMACK is V33_ATA_DMACK
--operation mode is output

V33_ATA_DMACK = OUTPUT(A1L75);


--V33_ATA_CS0 is V33_ATA_CS0
--operation mode is output

V33_ATA_CS0 = OUTPUT(A1L34);


--V33_ATA_CS1 is V33_ATA_CS1
--operation mode is output

V33_ATA_CS1 = OUTPUT(A1L54);


--V33_ATA_DIOR is V33_ATA_DIOR
--operation mode is output

V33_ATA_DIOR = OUTPUT(A1L35);


--V33_ATA_DIOW is V33_ATA_DIOW
--operation mode is output

V33_ATA_DIOW = OUTPUT(A1L55);


--V33_ATA_BUFF_DIR is V33_ATA_BUFF_DIR
--operation mode is output

V33_ATA_BUFF_DIR = OUTPUT(ATA_DIR);


--V33_ATA_BUFF_ENZ is V33_ATA_BUFF_ENZ
--operation mode is output

V33_ATA_BUFF_ENZ = OUTPUT(ATA_SEL);


--V33_ATA_RESETn is V33_ATA_RESETn
--operation mode is output

V33_ATA_RESETn = OUTPUT(V18_SYS_RESETZ);


--V33_SYS_RESETZ is V33_SYS_RESETZ
--operation mode is output

V33_SYS_RESETZ = OUTPUT(V18_SYS_RESETZ);


--V33_UART_TXD1 is V33_UART_TXD1
--operation mode is output

V33_UART_TXD1 = OUTPUT(OPNDRN(VCC));