📄 muxcntlr.tan.rpt
字号:
; N/A ; None ; 5.944 ns ; V33_SM_WAIT_BUSY ; WAIT_BUSY ;
; N/A ; None ; 5.896 ns ; READ_OE ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 5.851 ns ; V33_SM_CEZ ; WAIT_BUSY ;
; N/A ; None ; 5.845 ns ; V33_SM_CEZ ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 5.837 ns ; NAND_BUSY ; WAIT_BUSY ;
; N/A ; None ; 5.832 ns ; V33_ATA_WAIT_BUSY ; WAIT_BUSY ;
; N/A ; None ; 5.797 ns ; V33_CF_PWR_ON ; INTRQ_EM_RNW ;
; N/A ; None ; 5.694 ns ; ATA_SEL ; WAIT_BUSY ;
; N/A ; None ; 5.648 ns ; ATA_SEL ; UART_RXD1_DMARQ ;
; N/A ; None ; 5.548 ns ; V33_CF_INTRQ_EM_RNW ; INTRQ_EM_RNW ;
; N/A ; None ; 5.548 ns ; ATA_DIR ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 5.543 ns ; CFN_SEL ; INTRQ_EM_RNW ;
; N/A ; None ; 5.364 ns ; ATA_SEL ; V33_ATA_DA2 ;
; N/A ; None ; 5.345 ns ; V33_ATA_DMARQ ; UART_RXD1_DMARQ ;
; N/A ; None ; 5.337 ns ; ATA_SEL ; V33_ATA_DIOW ;
; N/A ; None ; 5.322 ns ; WRITE_WE ; V33_ATA_DIOW ;
; N/A ; None ; 5.314 ns ; V33_CF_WAIT_BUSY ; WAIT_BUSY ;
; N/A ; None ; 5.253 ns ; ATA_SEL ; INTRQ_EM_RNW ;
; N/A ; None ; 5.184 ns ; V33_ATA_INTRQ_EM_RNW ; INTRQ_EM_RNW ;
; N/A ; None ; 5.053 ns ; UART_TXD1_DMACK ; V33_ATA_DMACK ;
; N/A ; None ; 4.973 ns ; ATA_CS1 ; V33_ATA_CS1 ;
; N/A ; None ; 4.907 ns ; ATA2_EM_A0 ; V33_ATA_DA2 ;
; N/A ; None ; 4.903 ns ; ATA_CS0 ; V33_ATA_CS0 ;
; N/A ; None ; 4.844 ns ; READ_OE ; V33_ATA_DIOR ;
; N/A ; None ; 4.760 ns ; V33_CF_PWR_ON ; V33_CF_ATA_CS1 ;
; N/A ; None ; 4.760 ns ; V33_CF_PWR_ON ; V33_CF_ATA_CS0 ;
; N/A ; None ; 4.756 ns ; V33_CF_PWR_ON ; V33_CF_READ_OE ;
; N/A ; None ; 4.755 ns ; V33_CF_PWR_ON ; V33_CF_WRITE_WE ;
; N/A ; None ; 4.749 ns ; ATA1_EM_BA1 ; V33_CF_ATA1_EM_BA1 ;
; N/A ; None ; 4.739 ns ; V33_CF_PWR_ON ; V33_CF_ATA2_EM_A0 ;
; N/A ; None ; 4.734 ns ; V33_CF_PWR_ON ; V33_CF_ATA1_EM_BA1 ;
; N/A ; None ; 4.732 ns ; ATA2_EM_A0 ; V33_CF_ATA2_EM_A0 ;
; N/A ; None ; 4.705 ns ; ATA_CS0 ; V33_CF_ATA_CS0 ;
; N/A ; None ; 4.681 ns ; ATA_CS1 ; V33_CF_ATA_CS1 ;
; N/A ; None ; 4.676 ns ; ATA0_EM_BA0 ; V33_ATA_DA0 ;
; N/A ; None ; 4.660 ns ; ATA0_EM_BA0 ; V33_CF_ATA0_EM_BA0 ;
; N/A ; None ; 4.601 ns ; CFN_SEL ; V33_CF_ATA_CS0 ;
; N/A ; None ; 4.601 ns ; WRITE_WE ; V33_CF_WRITE_WE ;
; N/A ; None ; 4.599 ns ; CFN_SEL ; V33_CF_READ_OE ;
; N/A ; None ; 4.599 ns ; CFN_SEL ; V33_CF_WRITE_WE ;
; N/A ; None ; 4.598 ns ; CFN_SEL ; V33_CF_ATA_CS1 ;
; N/A ; None ; 4.576 ns ; ATA_DIR ; V33_ATA_BUFF_DIR ;
; N/A ; None ; 4.575 ns ; READ_OE ; V33_CF_READ_OE ;
; N/A ; None ; 4.554 ns ; WRITE_WE ; V33_SM_WRITE_WE ;
; N/A ; None ; 4.542 ns ; CFN_SEL ; V33_CF_ATA0_EM_BA0 ;
; N/A ; None ; 4.541 ns ; READ_OE ; V33_SM_READ_OE ;
; N/A ; None ; 4.536 ns ; ALE_EM_A1 ; V33_SM_ALE_EM_A1 ;
; N/A ; None ; 4.513 ns ; ATA1_EM_BA1 ; V33_ATA_DA1 ;
; N/A ; None ; 4.510 ns ; MSP430_INT_IN ; MSP430_INT_OUT ;
; N/A ; None ; 4.396 ns ; V33_CF_PWR_ON ; V33_CF_ATA0_EM_BA0 ;
; N/A ; None ; 4.368 ns ; ATA_SEL ; V33_ATA_DA1 ;
; N/A ; None ; 4.367 ns ; ATA_SEL ; V33_ATA_CS1 ;
; N/A ; None ; 4.366 ns ; ATA_SEL ; V33_ATA_DMACK ;
; N/A ; None ; 4.358 ns ; ATA_SEL ; V33_ATA_DA0 ;
; N/A ; None ; 4.356 ns ; ATA_SEL ; V33_ATA_DIOR ;
; N/A ; None ; 4.337 ns ; CFN_SEL ; V33_CF_ATA2_EM_A0 ;
; N/A ; None ; 4.333 ns ; CFN_SEL ; V33_CF_ATA1_EM_BA1 ;
; N/A ; None ; 4.292 ns ; ATA_SEL ; V33_ATA_CS0 ;
; N/A ; None ; 4.225 ns ; V33_SM_CEZ ; V33_SM_READ_OE ;
; N/A ; None ; 4.225 ns ; V33_SM_CEZ ; V33_SM_WRITE_WE ;
; N/A ; None ; 4.222 ns ; V33_SM_CEZ ; V33_SM_ALE_EM_A1 ;
; N/A ; None ; 4.221 ns ; V33_SM_CEZ ; V33_SM_CLE_EM_A2 ;
; N/A ; None ; 4.149 ns ; CLE_EM_A2 ; V33_SM_CLE_EM_A2 ;
; N/A ; None ; 3.914 ns ; V18_SYS_RESETZ ; V33_ATA_RESETn ;
; N/A ; None ; 3.871 ns ; V18_SYS_RESETZ ; V33_SYS_RESETZ ;
; N/A ; None ; 3.790 ns ; V33_SM_CEZ ; V33_SM_SM_CEZ ;
; N/A ; None ; 3.683 ns ; ATA_SEL ; V33_ATA_BUFF_ENZ ;
+-------+-------------------+-----------------+----------------------+---------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Nov 10 15:38:55 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off muxcntlr -c muxcntlr
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "V33_TIMER_IN" is an undefined clock
Info: Clock "V33_TIMER_IN" Internal fmax is restricted to 304.04 MHz between source register "div8[1]" and destination register "div8[2]"
Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.121 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; REG Node = 'div8[1]'
Info: 2: + IC(0.807 ns) + CELL(0.125 ns) = 0.932 ns; Loc. = LC_X4_Y1_N8; Fanout = 1; COMB Node = 'add~38'
Info: 3: + IC(0.412 ns) + CELL(0.777 ns) = 2.121 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8[2]'
Info: Total cell delay = 0.902 ns ( 42.53 % )
Info: Total interconnect delay = 1.219 ns ( 57.47 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "V33_TIMER_IN" to destination register is 2.162 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'
Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8[2]'
Info: Total cell delay = 1.301 ns ( 60.18 % )
Info: Total interconnect delay = 0.861 ns ( 39.82 % )
Info: - Longest clock path from clock "V33_TIMER_IN" to source register is 2.162 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'
Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; REG Node = 'div8[1]'
Info: Total cell delay = 1.301 ns ( 60.18 % )
Info: Total interconnect delay = 0.861 ns ( 39.82 % )
Info: + Micro clock to output delay of source is 0.235 ns
Info: + Micro setup delay of destination is 0.208 ns
Info: tco from clock "V33_TIMER_IN" to destination pin "CPLD_TIMER_OUT" through register "div8[2]" is 5.193 ns
Info: + Longest clock path from clock "V33_TIMER_IN" to source register is 2.162 ns
Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_62; Fanout = 3; CLK Node = 'V33_TIMER_IN'
Info: 2: + IC(0.861 ns) + CELL(0.574 ns) = 2.162 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8[2]'
Info: Total cell delay = 1.301 ns ( 60.18 % )
Info: Total interconnect delay = 0.861 ns ( 39.82 % )
Info: + Micro clock to output delay of source is 0.235 ns
Info: + Longest register to pin delay is 2.796 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N6; Fanout = 2; REG Node = 'div8[2]'
Info: 2: + IC(0.484 ns) + CELL(2.312 ns) = 2.796 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'CPLD_TIMER_OUT'
Info: Total cell delay = 2.312 ns ( 82.69 % )
Info: Total interconnect delay = 0.484 ns ( 17.31 % )
Info: Longest tpd from source pin "ATA_SEL" to destination pin "V18_EM_DATA_BUF_DIR" is 6.724 ns
Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_54; Fanout = 14; PIN Node = 'ATA_SEL'
Info: 2: + IC(2.022 ns) + CELL(0.125 ns) = 2.855 ns; Loc. = LC_X3_Y4_N9; Fanout = 2; COMB Node = 'V18_EM_DATA_BUF_DIR~68'
Info: 3: + IC(1.021 ns) + CELL(0.125 ns) = 4.001 ns; Loc. = LC_X2_Y4_N2; Fanout = 1; COMB Node = 'V18_EM_DATA_BUF_DIR~69'
Info: 4: + IC(0.411 ns) + CELL(2.312 ns) = 6.724 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'V18_EM_DATA_BUF_DIR'
Info: Total cell delay = 3.270 ns ( 48.63 % )
Info: Total interconnect delay = 3.454 ns ( 51.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Nov 10 15:38:56 2005
Info: Elapsed time: 00:00:01
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