📄 muxcntlr.tan.rpt
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Timing Analyzer report for muxcntlr
Thu Nov 10 15:38:56 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'V33_TIMER_IN'
6. tco
7. tpd
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------------------+--------------+--------------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------------------+--------------+--------------+--------------+
; Worst-case tco ; N/A ; None ; 5.193 ns ; div8[2] ; CPLD_TIMER_OUT ; V33_TIMER_IN ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 6.724 ns ; ATA_SEL ; V18_EM_DATA_BUF_DIR ; ; ; 0 ;
; Clock Setup: 'V33_TIMER_IN' ; N/A ; None ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[1] ; div8[2] ; V33_TIMER_IN ; V33_TIMER_IN ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------------------+--------------+--------------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240GT100C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; V33_TIMER_IN ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'V33_TIMER_IN' ;
+-------+------------------------------------------------+---------+---------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+---------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[1] ; div8[2] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 2.121 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[0] ; div8[2] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 2.116 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[0] ; div8[1] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 1.557 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[0] ; div8[0] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 1.107 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[2] ; div8[2] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 1.101 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; div8[1] ; div8[1] ; V33_TIMER_IN ; V33_TIMER_IN ; None ; None ; 0.927 ns ;
+-------+------------------------------------------------+---------+---------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+----------------+--------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+----------------+--------------+
; N/A ; None ; 5.193 ns ; div8[2] ; CPLD_TIMER_OUT ; V33_TIMER_IN ;
+-------+--------------+------------+---------+----------------+--------------+
+------------------------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+----------------------+---------------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+----------------------+---------------------+
; N/A ; None ; 6.724 ns ; ATA_SEL ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 6.625 ns ; ATA_SEL ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.569 ns ; CFN_SEL ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 6.484 ns ; EM_CS2 ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.480 ns ; ATA_CS0 ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.470 ns ; CFN_SEL ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.411 ns ; ATA_CS1 ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.285 ns ; UART_TXD1_DMACK ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.283 ns ; EM_CS2 ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 6.266 ns ; V33_CF_PWR_ON ; WAIT_BUSY ;
; N/A ; None ; 6.252 ns ; READ_OE ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.243 ns ; V33_CF_PWR_ON ; V18_EM_DATA_BUF_DIR ;
; N/A ; None ; 6.144 ns ; V33_CF_PWR_ON ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.046 ns ; V33_SM_CEZ ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.022 ns ; WRITE_WE ; V18_EM_DATA_BUF_EN ;
; N/A ; None ; 6.012 ns ; CFN_SEL ; WAIT_BUSY ;
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