muxcntlr.map.talkback.xml

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<!--
This XML file (created on Mon Oct 03 13:07:08 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.0</ver>
<schema>quartus_version_5.0_build_168.xsd</schema><license>
	<host_id>00123f10f9bb</host_id>
	<nic_id>0012f0ab0081</nic_id>
	<cdrive_id>7c593b76</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.0</version>
	<build>Build 168 SP 1</build>
	<module>quartus_map.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Mon Oct 03 13:07:08 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1594</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>C:/fpga/davinci_evm/muxcntlr/muxcntlr</top_file>
<eda_tools>
	<eda_tool type="eda_design_synthesis">SYNPLIFY</eda_tool>
	<eda_tool type="eda_simulation">ModelSim-Altera (VHDL output from Quartus II)</eda_tool>
</eda_tools>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off muxcntlr -c muxcntlr</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EPM240GT100C3</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>muxcntlr</setting>
		<default_value>muxcntlr</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>MAX II</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Type of Retiming Performed During Resynthesis</option>
		<setting>Full</setting>
	</row>
	<row>
		<option>Resynthesis Optimization Effort</option>
		<setting>Normal</setting>
	</row>
	<row>
		<option>Physical Synthesis Level for Resynthesis</option>
		<setting>Normal</setting>
	</row>
	<row>
		<option>Use Generated Physical Constraints File</option>
		<setting>On</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Restructure Multiplexers</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>off</setting>
		<default_value>off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- MAX II</option>
		<setting>Balanced</setting>
		<default_value>Balanced</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
		<setting>70</setting>
		<default_value>70</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform WYSIWYG Primitive Resynthesis</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform gate-level register retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Shift Register Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Allows Synchronous Control Signal Usage in Normal Mode Logic Cells</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Block Balancing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Number of M512 Memory Blocks</option>
		<setting>-1</setting>
		<default_value>-1</default_value>
	</row>
	<row>
		<option>Maximum Number of M4K Memory Blocks</option>
		<setting>-1</setting>
		<default_value>-1</default_value>
	</row>
	<row>
		<option>Maximum Number of M-RAM Memory Blocks</option>
		<setting>-1</setting>
		<default_value>-1</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</analysis___synthesis_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<compilation_summary>
	<flow_status>Successful - Mon Oct 03 13:07:08 2005</flow_status>
	<quartus_ii_version>5.0 Build 168 06/22/2005 SP 1 SJ Web Edition</quartus_ii_version>
	<revision_name>muxcntlr</revision_name>
	<top_level_entity_name>muxcntlr</top_level_entity_name>
	<family>MAX II</family>
	<device>EPM240GT100C3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>29</total_logic_elements>
	<total_pins>56</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<ufm_blocks>0</ufm_blocks>
</compilation_summary>
<compile_id>24A0A231</compile_id>
</talkback>