📄 muxcntlr.fit.talkback.xml
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<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_ATA_DA2</name>
<pin__>67</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>3</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_ATA_DIOR</name>
<pin__>71</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>4</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_ATA_DIOW</name>
<pin__>72</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>4</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_ATA_DMACK</name>
<pin__>68</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>3</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_ATA_RESETn</name>
<pin__>73</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>4</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_ATA0_EM_BA0</name>
<pin__>89</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>4</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_ATA1_EM_BA1</name>
<pin__>90</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>4</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_ATA2_EM_A0</name>
<pin__>91</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>4</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_ATA_CS0</name>
<pin__>87</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_ATA_CS1</name>
<pin__>88</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_READ_OE</name>
<pin__>86</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_CF_WRITE_WE</name>
<pin__>85</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SM_ALE_EM_A1</name>
<pin__>92</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>3</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SM_CLE_EM_A2</name>
<pin__>95</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>3</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SM_READ_OE</name>
<pin__>97</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>3</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SM_SM_CEZ</name>
<pin__>98</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>2</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SM_WRITE_WE</name>
<pin__>96</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>3</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_SYS_RESETZ</name>
<pin__>53</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>8</x_coordinate>
<y_coordinate>1</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>V33_UART_TXD1</name>
<pin__>78</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>7</x_coordinate>
<y_coordinate>5</y_coordinate>
<cell_number>3</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>16mA</current_strength>
<fast_output_connection>no</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
<row>
<name>WAIT_BUSY</name>
<pin__>42</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>5</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>yes</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>1.8 V</i_o_standard>
<current_strength>6mA</current_strength>
<fast_output_connection>yes</fast_output_connection>
<location_assigned_by>User</location_assigned_by>
<load units="pF">10</load>
</row>
</output_pins>
<compilation_summary>
<flow_status>Successful - Mon Oct 03 13:07:11 2005</flow_status>
<quartus_ii_version>5.0 Build 168 06/22/2005 SP 1 SJ Web Edition</quartus_ii_version>
<revision_name>muxcntlr</revision_name>
<top_level_entity_name>muxcntlr</top_level_entity_name>
<family>MAX II</family>
<device>EPM240GT100C3</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>29 / 240 ( 12 % )</total_logic_elements>
<total_pins>56 / 80 ( 70 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<ufm_blocks>0 / 1 ( 0 % )</ufm_blocks>
</compilation_summary>
<compile_id>542C8886</compile_id>
<files>
<top>C:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd</top>
<extensions>
<ext ext_name="vhd">1</ext>
</extensions>
<sub_files>
<sub_file>C:/fpga/davinci_evm/muxcntlr/muxcntlr.vhd</sub_file>
</sub_files>
</files>
<architecture>
<family>MAX II</family>
<auto_device>OFF</auto_device>
<device>EPM240GT100C3</device>
</architecture>
<pkg_io>
<pin_std count="37">LVTTL</pin_std>
<pin_std count="19">1.8 V</pin_std>
</pkg_io>
<research>
<le_sclr>0</le_sclr>
<le_aclr>0</le_aclr>
<le_aload>0</le_aload>
<le_sload>0</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>0</le_carry_in>
<le_ce>0</le_ce>
<le_clk>0</le_clk>
<le_ce_sload>0</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
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