muxcntlr.fit.talkback.xml

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		<y_coordinate>1</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>MSP430_INT_IN</name>
		<pin__>52</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>1</y_coordinate>
		<cell_number>4</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>READ_OE</name>
		<pin__>17</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>3</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>UART_TXD1_DMACK</name>
		<pin__>26</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V18_SYS_RESETZ</name>
		<pin__>51</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_ATA_DMARQ</name>
		<pin__>56</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>1</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_ATA_INTRQ_EM_RNW</name>
		<pin__>57</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_ATA_WAIT_BUSY</name>
		<pin__>58</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_CF_INTRQ_EM_RNW</name>
		<pin__>83</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>6</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_CF_PWR_ON</name>
		<pin__>100</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>11</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_CF_WAIT_BUSY</name>
		<pin__>84</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>6</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_SM_CEZ</name>
		<pin__>1</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>7</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_SM_WAIT_BUSY</name>
		<pin__>99</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>V33_UART_RXD1</name>
		<pin__>77</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>WRITE_WE</name>
		<pin__>16</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>3</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>INTRQ_EM_RNW</name>
		<pin__>38</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>4</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>yes</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<current_strength>6mA</current_strength>
		<fast_output_connection>yes</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>MSP430_INT_OUT</name>
		<pin__>39</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>5</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<current_strength>6mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>UART_RXD1_DMARQ</name>
		<pin__>27</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<current_strength>6mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V18_EM_DATA_BUF_DIR</name>
		<pin__>2</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<current_strength>6mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V18_EM_DATA_BUF_EN</name>
		<pin__>3</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>1.8 V</i_o_standard>
		<current_strength>6mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_BUFF_DIR</name>
		<pin__>74</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_BUFF_ENZ</name>
		<pin__>75</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_CS0</name>
		<pin__>61</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_CS1</name>
		<pin__>66</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_DA0</name>
		<pin__>70</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>4</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>V33_ATA_DA1</name>
		<pin__>69</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>