st_ext32.asm

本程序通过现场实验应用在TI的DSP2407通讯 没有问题可以适宜市

* PROGRAM TO DEMONSTRATE THE SELF-TEST MODE IN 24x/240xA CAN *
* Simple loop back test: the CAN sends a message to itself. 
; MAILBOX 3 for TRANSMISSION / MAILBOX 2 for RECEPTION
	
	.include    "240x.h"		; Variable and register declaration
    .include    "vector.h"		; Vector table (takes care of dummy password)
    .global		START

;-----------------------------------------------------------
; Other constant definitions
;-----------------------------------------------------------	 
DP_PF1		.set	224	; Page 1 of peripheral file (7000h/80h
DP_CAN		.set	0E2h    ; Can Registers (7100h)
DP_CAN2		.set	0E4h   	; Can RAM (7200h)

KICK_DOG	.macro				;Watchdog reset macro
		LDP		#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP		#0h
		.endm

;=======================================================================
; M A I N   C O D E  - starts here
;=======================================================================
		.text
START:	KICK_DOG                ; Reset Watchdog counter
		SPLK	#0,60h
		OUT		60h,WSGR		; Set waitstates for external memory (if used)
		SETC	INTM    		; Disable interrupts
		SPLK	#0000h,IMR		; Mask all core interrupts
		LDP		#0E0h
		SPLK	#006Fh, WDCR	; Disable WD 
		SPLK	#0010h,SCSR1	; Enable clock to CAN module (For 240xA only)
		
		LAR		AR1,#300h		; AR1 => Copy CAN RAM (B0)
		LAR		AR2,#7214h		; AR2 => Mailbox 2 RAM (Rcv)
		LAR		AR4,#721ch      ; AR4 => Mailbox 3 RAM (Xmi)
		LAR		AR3,#3			; AR3 => counter
	   	LAR		AR5,#7100h		; AR5 => CAN control registers
       

		LDP 	#DP_CAN	
		SPLK	#03f7fh,CANIMR					; Enable all ints.

;**************************************************************************
;******     DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL 	  **********
;**************************************************************************	
	   
	   	SPLK	#0000000000000000b,CANMDER  ; Disable all mailboxes
;				 ||||||||||||||||	     	; Required b4 writing 
;			 	 FEDCBA9876543210	     	; to MBX RAM
		
;**************************************************************************
;***********          SET MSGIDs OF CAN MAILBOXES                **********
;**************************************************************************

		LDP	#DP_CAN2
			
		SPLK	#1111111111111111b,CANMSGID2H     ; Set mailbox 2 ID
;		  	 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit
			
		SPLK	#1111111111111010b,CANMSGID2L	 ; 1FFF FFFA --> ID	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 0-15	lower part of extended identifier		
;----------------------------------------------------------------------------		
		SPLK	#1111111111111111b,CANMSGID3H   ; Set mailbox 3 ID
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit

		SPLK	#1111111111111010b,CANMSGID3L	; 1FFF FFFA --> ID
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;**************************************************************************
;***********                Write CAN Mailboxes                  **********
;**************************************************************************

;bit 0-15	lower part of extended identifier
;----------------------------------------------------------------------------
		SPLK	#0000000000001000b,CANMSGCTRL3
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-3	Data length code: 1000 = 8 bytes
;bit 4		0: data frame 

		SPLK	#00123h,CANMBX3A	; Message to transmit
		SPLK	#04567h,CANMBX3B
		SPLK	#089ABh,CANMBX3C	   	
		SPLK	#0CDEFh,CANMBX3D

LOOP_READ2  	MAR	*,AR4			; AR4 => Mailbox 3 RAM (Xmi)
	   	LACL	*+,AR1  		; Copy the Mailbox 0 in ACC
 		SACL	*+,AR3			; Copy the Mailbox 0 in B0
   		BANZ	LOOP_READ2   
		LAR		AR3,#0Bh		;AR3 => counter		
		        
;**************************************************************************
;***********    Enable Mailboxes after writing     **********
;**************************************************************************

		LDP 	#DP_CAN	
		
		SPLK	#0000000001001100b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	enable mailboxes 3 and 2 
;bit 6		1: mailbox 2 receive 
;bit 7 		0: mailbox 3 transmit

;**************************************************************************
;***********    Bit timing Registers configuration   **********************
;**************************************************************************
		
		LDP 	#DP_CAN	
		SPLK	#0001000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 12		Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,#0Bh	; Wait for Change config Enable
		BCND	W_CCE,NTC	; bit to be set in GSR
         
        ;SPLK	#0000000000000000b,CANBCR2     ; For 1 M bits/s @ 20 MHz CLKOUT
        SPLK	#0000000000000001b,CANBCR2     ; For 1 M bits/s @ 40 MHz CLKOUT
;			 	 ||||||||||||||||
;			     FEDCBA9876543210 

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved
	    
		SPLK	#0000000011111010b,CANBCR1     ; For 1 M bits/s @ 85 % samp. pt
;			 	 ||||||||||||||||
;			  	 FEDCBA9876543210  

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 

		SPLK	#0000000001000000b,CANMCR 	; Enable self-test mode
;			  	 ||||||||||||||||
;			  	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh	; Wait for Change config disable
		BCND	W_NCCE,TC
		
;**************************************************************************
;***********                      TRANSMIT                      **********
;**************************************************************************
		SPLK	#0020h,CANTCR	; transmit request for mailbox 3           
			
W_TA	BIT		CANTCR,2		; Wait for transmission acknowledge
		BCND	W_TA,NTC						

COPY    MAR		*,AR5			; AR5 => CAN control registers
	   	LACL	*+,AR1  		; Copy the CAN control regs in Accu
 		SACL	*+,AR3			; Copy the CAN control regsin B0
   		BANZ	COPY			; 11 times 
		
W_FLAG3	BIT		CANIFR,4		; wait for interrupt flag
		BCND	W_FLAG3,NTC			
		SPLK	#2000h,CANTCR	; reset TA and CANIFR 

;**************************************************************************
;***********                       RECEIVE                     **********
;**************************************************************************
W_FLAG2	BIT		CANIFR,BIT10	; Wait for MBX2 RCV interrupt 
		BCND	W_FLAG2,NTC			
		
W_RA	BIT		CANRCR,9		; Wait for receive acknowledge
		BCND	W_RA,NTC		; RMP bit set for MBX2?
		SPLK	#0040h,CANRCR	; reset RMP and CANIFR 		
		
;**************************************************************************
;***********                READ CAN RAM                       **********
;**************************************************************************
		
	    LAR		AR3,#3h			; AR3->3

LOOP_READ  	MAR	*,AR2			; AR2 => Mailbox 2 RAM (Rcv)
	   	LACL	*+,AR1  		; Copy MBX 2 in Accu
 		SACL	*+,AR3			; Copy MBX 2 in B0
   		BANZ	LOOP_READ		; 

LOOP		B	LOOP			; loop	

GISR1:	RET
GISR2:	RET
GISR3:	RET
GISR4:	RET
GISR5:	RET
GISR6:	RET
PHANTOM:	RET

; When program works correctly,
; mailbox data will be seen beginning in 300h and 310h. The transmitted data is
; stored beginning at 300h and the received data is stored beginning at 310h.
; If things are ok, the transmitted & received data should be the same.