adder8b.rpt

来自「8位加法器VHDL 8位加法器VHDL 8位加法器VHDL」· RPT 代码 · 共 647 行 · 第 1/2 页

RPT
647
字号
        | | | | | | | | | | | +------- LC18 S82
        | | | | | | | | | | | | +----- LC22 S83
        | | | | | | | | | | | | | +--- LC23 S84
        | | | | | | | | | | | | | | +- LC25 S85
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC32 -> - - - - - * - - - - - - - - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
LC31 -> - - - - - - * - - - - - - - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
LC29 -> - - - - - - * - - * * * * - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
LC26 -> - - - - - - * - - - - * * - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
LC28 -> - - - - - - * - - - - * * - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
LC27 -> - - - - - - * - - - - - * - - | - * | <-- |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
LC20 -> - - - - - - - - - - - - - * * | * * | <-- |adder4b:U1|LPM_ADD_SUB:47|addcore:adder|addcore:adder0|result_node4
LC24 -> - - - - - - - - - - - - - * * | * * | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0

Pin
19   -> * * * * * - - - - - * - - - - | - * | <-- A80
18   -> * * - * * - - - - - * - - - - | - * | <-- A81
8    -> * * - - * - - - - - - - - - - | - * | <-- A82
9    -> - * - - - * - - - - - - - - - | - * | <-- A83
31   -> - - - - - - - * * - - - - - * | * * | <-- A84
7    -> - - - - - - - - * - - - - - * | * * | <-- A85
13   -> * * * * * - - - - - * - - - - | - * | <-- B80
14   -> * * - * * - - - - - * - - - - | - * | <-- B81
20   -> * * - - * - - - - - - - - - - | - * | <-- B82
41   -> - * - - - * - - - - - - - - - | - * | <-- B83
33   -> - - - - - - - * * - - - - - * | * * | <-- B84
38   -> - - - - - - - - * - - - - - * | * * | <-- B85
21   -> - - - - - - * - - * * * * - - | - * | <-- C8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            c:\adder8b\adder8b.rpt
adder8b

** EQUATIONS **

A80      : INPUT;
A81      : INPUT;
A82      : INPUT;
A83      : INPUT;
A84      : INPUT;
A85      : INPUT;
A86      : INPUT;
A87      : INPUT;
B80      : INPUT;
B81      : INPUT;
B82      : INPUT;
B83      : INPUT;
B84      : INPUT;
B85      : INPUT;
B86      : INPUT;
B87      : INPUT;
C8       : INPUT;

-- Node name is 'CO8' 
-- Equation name is 'CO8', location is LC003, type is output.
 CO8     = LCELL( _LC004 $  _EQ001);
  _EQ001 =  _LC005 &  _LC006 &  _LC020 &  _LC024 &  _LC030;

-- Node name is 'S80' 
-- Equation name is 'S80', location is LC021, type is output.
 S80     = LCELL( C8 $  _LC029);

-- Node name is 'S81' 
-- Equation name is 'S81', location is LC019, type is output.
 S81     = LCELL( _EQ002 $  _EQ003);
  _EQ002 =  A80 &  A81 &  B80 &  B81
         #  A80 & !A81 &  B80 & !B81
         # !A80 &  _X001 &  _X002
         # !B80 &  _X001 &  _X002;
  _X001  = EXP( A81 &  B81);
  _X002  = EXP(!A81 & !B81);
  _EQ003 =  C8 &  _LC029;

-- Node name is 'S82' 
-- Equation name is 'S82', location is LC018, type is output.
 S82     = LCELL( _LC028 $  _EQ004);
  _EQ004 =  C8 &  _LC026 &  _LC029;

-- Node name is 'S83' 
-- Equation name is 'S83', location is LC022, type is output.
 S83     = LCELL( _LC027 $  _EQ005);
  _EQ005 =  C8 &  _LC026 &  _LC028 &  _LC029;

-- Node name is 'S84' 
-- Equation name is 'S84', location is LC023, type is output.
 S84     = LCELL( _LC020 $  _LC024);

-- Node name is 'S85' 
-- Equation name is 'S85', location is LC025, type is output.
 S85     = LCELL( _EQ006 $  _EQ007);
  _EQ006 =  A84 &  A85 &  B84 &  B85
         #  A84 & !A85 &  B84 & !B85
         # !A84 &  _X003 &  _X004
         # !B84 &  _X003 &  _X004;
  _X003  = EXP( A85 &  B85);
  _X004  = EXP(!A85 & !B85);
  _EQ007 =  _LC020 &  _LC024;

-- Node name is 'S86' 
-- Equation name is 'S86', location is LC001, type is output.
 S86     = LCELL( _LC005 $  _EQ008);
  _EQ008 =  _LC020 &  _LC024 &  _LC030;

-- Node name is 'S87' 
-- Equation name is 'S87', location is LC002, type is output.
 S87     = LCELL( _LC006 $  _EQ009);
  _EQ009 =  _LC005 &  _LC020 &  _LC024 &  _LC030;

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC032', type is buried 
_LC032   = LCELL( _EQ010 $  GND);
  _EQ010 =  A80 &  B80 &  _X002 &  _X005
         #  A81 &  B81 &  _X005
         #  A82 &  B82;
  _X002  = EXP(!A81 & !B81);
  _X005  = EXP(!A82 & !B82);

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC031', type is buried 
_LC031   = LCELL( _EQ011 $  _EQ012);
  _EQ011 =  A80 &  B80 &  _X002 &  _X005 &  _X006 &  _X007
         #  A81 &  B81 &  _X005 &  _X006 &  _X007
         #  A82 &  B82 &  _X006 &  _X007;
  _X002  = EXP(!A81 & !B81);
  _X005  = EXP(!A82 & !B82);
  _X006  = EXP(!A83 & !B83);
  _X007  = EXP( A83 &  B83);
  _EQ012 =  A83 &  B83;

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( B80 $  A80);

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( _EQ013 $  GND);
  _EQ013 =  A80 &  A81 &  B80 &  B81
         #  A80 & !A81 &  B80 & !B81
         # !A80 &  _X001 &  _X002
         # !B80 &  _X001 &  _X002;
  _X001  = EXP( A81 &  B81);
  _X002  = EXP(!A81 & !B81);

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( _EQ014 $  _EQ015);
  _EQ014 =  A80 &  B80 &  _X002
         #  A81 &  B81;
  _X002  = EXP(!A81 & !B81);
  _EQ015 =  _X005 &  _X008;
  _X005  = EXP(!A82 & !B82);
  _X008  = EXP( A82 &  B82);

-- Node name is '|adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( _EQ016 $  _LC032);
  _EQ016 =  _X006 &  _X007;
  _X006  = EXP(!A83 & !B83);
  _X007  = EXP( A83 &  B83);

-- Node name is '|adder4b:U1|LPM_ADD_SUB:47|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( _LC031 $  _EQ017);
  _EQ017 =  C8 &  _LC026 &  _LC027 &  _LC028 &  _LC029;

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC010', type is buried 
_LC010   = LCELL( _EQ018 $  GND);
  _EQ018 =  A84 &  B84 &  _X004 &  _X009
         #  A85 &  B85 &  _X009
         #  A86 &  B86;
  _X004  = EXP(!A85 & !B85);
  _X009  = EXP(!A86 & !B86);

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC004', type is buried 
_LC004   = LCELL( _EQ019 $  _EQ020);
  _EQ019 =  A84 &  B84 &  _X004 &  _X009 &  _X010 &  _X011
         #  A85 &  B85 &  _X009 &  _X010 &  _X011
         #  A86 &  B86 &  _X010 &  _X011;
  _X004  = EXP(!A85 & !B85);
  _X009  = EXP(!A86 & !B86);
  _X010  = EXP( A87 &  B87);
  _X011  = EXP(!A87 & !B87);
  _EQ020 =  A87 &  B87;

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( B84 $  A84);

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( _EQ021 $  GND);
  _EQ021 =  A84 &  A85 &  B84 &  B85
         #  A84 & !A85 &  B84 & !B85
         # !A84 &  _X003 &  _X004
         # !B84 &  _X003 &  _X004;
  _X003  = EXP( A85 &  B85);
  _X004  = EXP(!A85 & !B85);

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC005', type is buried 
_LC005   = LCELL( _EQ022 $  _EQ023);
  _EQ022 =  A84 &  B84 &  _X004
         #  A85 &  B85;
  _X004  = EXP(!A85 & !B85);
  _EQ023 =  _X009 &  _X012;
  _X009  = EXP(!A86 & !B86);
  _X012  = EXP( A86 &  B86);

-- Node name is '|adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC006', type is buried 
_LC006   = LCELL( _EQ024 $  _LC010);
  _EQ024 =  _X010 &  _X011;
  _X010  = EXP( A87 &  B87);
  _X011  = EXP(!A87 & !B87);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X004 occurs in LABs A, B




Project Information                                     c:\adder8b\adder8b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,740K

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