adder8b.rpt
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RPT
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Project Information c:\adder8b\adder8b.rpt
MAX+plus II Compiler Report File
Version 10.23 07/09/2003
Compiled: 04/19/2007 05:45:07
Copyright (C) 1988-2003 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ADDER8B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
adder8b EPM7032LC44-6 17 9 0 22 13 68 %
User Pins: 17 9 0
Project Information c:\adder8b\adder8b.rpt
** FILE HIERARCHY **
|adder4b:U1|
|adder4b:U1|lpm_add_sub:46|
|adder4b:U1|lpm_add_sub:46|addcore:adder|
|adder4b:U1|lpm_add_sub:46|addcore:adder|addcore:adder0|
|adder4b:U1|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|adder4b:U1|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|adder4b:U1|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|adder4b:U1|lpm_add_sub:47|
|adder4b:U1|lpm_add_sub:47|addcore:adder|
|adder4b:U1|lpm_add_sub:47|addcore:adder|addcore:adder0|
|adder4b:U1|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|adder4b:U1|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|adder4b:U1|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|adder4b:U2|
|adder4b:U2|lpm_add_sub:46|
|adder4b:U2|lpm_add_sub:46|addcore:adder|
|adder4b:U2|lpm_add_sub:46|addcore:adder|addcore:adder0|
|adder4b:U2|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|adder4b:U2|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|adder4b:U2|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|adder4b:U2|lpm_add_sub:47|
|adder4b:U2|lpm_add_sub:47|addcore:adder|
|adder4b:U2|lpm_add_sub:47|addcore:adder|addcore:adder0|
|adder4b:U2|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|adder4b:U2|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|adder4b:U2|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
***** Logic for device 'adder8b' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
C S S V G G G G G B S
O 8 8 C N N N N N 8 8
8 7 6 C D D D D D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
A85 | 7 39 | S81
A82 | 8 38 | B85
A83 | 9 37 | S80
GND | 10 36 | S83
A86 | 11 35 | VCC
A87 | 12 EPM7032LC44-6 34 | S84
B80 | 13 33 | B84
B81 | 14 32 | S85
VCC | 15 31 | A84
B87 | 16 30 | GND
B86 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
A A B C G V R R R R R
8 8 8 8 N C E E E E E
1 0 2 D C S S S S S
E E E E E
R R R R R
V V V V V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 16/16(100%) 5/16( 31%) 15/36( 41%)
B: LC17 - LC32 15/16( 93%) 10/16( 62%) 10/16( 62%) 21/36( 58%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 22/32 ( 68%)
Total shareable expanders used: 13/32 ( 40%)
Total Turbo logic cells used: 22/32 ( 68%)
Total shareable expanders not available (n/a): 2/32 ( 6%)
Average fan-in: 4.72
Total fan-in: 104
Total input pins required: 17
Total output pins required: 9
Total bidirectional pins required: 0
Total logic cells required: 22
Total flipflops required: 0
Total product terms required: 75
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
19 (14) (A) INPUT 0 0 0 0 0 1 5 A80
18 (13) (A) INPUT 0 0 0 0 0 1 4 A81
8 (5) (A) INPUT 0 0 0 0 0 0 3 A82
9 (6) (A) INPUT 0 0 0 0 0 0 2 A83
31 (26) (B) INPUT 0 0 0 0 0 1 5 A84
7 (4) (A) INPUT 0 0 0 0 0 1 4 A85
11 (7) (A) INPUT 0 0 0 0 0 0 3 A86
12 (8) (A) INPUT 0 0 0 0 0 0 2 A87
13 (9) (A) INPUT 0 0 0 0 0 1 5 B80
14 (10) (A) INPUT 0 0 0 0 0 1 4 B81
20 (15) (A) INPUT 0 0 0 0 0 0 3 B82
41 (17) (B) INPUT 0 0 0 0 0 0 2 B83
33 (24) (B) INPUT 0 0 0 0 0 1 5 B84
38 (20) (B) INPUT 0 0 0 0 0 1 4 B85
17 (12) (A) INPUT 0 0 0 0 0 0 3 B86
16 (11) (A) INPUT 0 0 0 0 0 0 2 B87
21 (16) (A) INPUT 0 0 0 0 0 4 1 C8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
6 3 A OUTPUT t 0 0 0 0 6 0 0 CO8
37 21 B OUTPUT t 0 0 0 1 1 0 0 S80
39 19 B OUTPUT t 3 2 1 5 1 0 0 S81
40 18 B OUTPUT t 0 0 0 1 3 0 0 S82
36 22 B OUTPUT t 0 0 0 1 4 0 0 S83
34 23 B OUTPUT t 0 0 0 0 2 0 0 S84
32 25 B OUTPUT t 3 2 1 4 2 0 0 S85
4 1 A OUTPUT t 0 0 0 0 4 0 0 S86
5 2 A OUTPUT t 0 0 0 0 5 0 0 S87
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT t 2 2 0 6 0 0 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
(25) 31 B SOFT t 4 4 0 8 0 0 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
(27) 29 B SOFT t 0 0 0 2 0 4 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
(31) 26 B SOFT t 2 2 0 4 0 2 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
(28) 28 B SOFT t 3 2 0 6 0 2 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
(29) 27 B SOFT t 2 2 0 2 1 1 1 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
(38) 20 B SOFT t 0 0 0 1 5 5 0 |adder4b:U1|LPM_ADD_SUB:47|addcore:adder|addcore:adder0|result_node4
(14) 10 A SOFT t 2 2 0 6 0 0 1 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
(7) 4 A SOFT t 4 4 0 8 0 1 0 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
(33) 24 B SOFT t 0 0 0 2 0 5 0 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
(26) 30 B SOFT t 2 2 0 4 0 3 0 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
(8) 5 A SOFT t 3 2 0 6 0 3 0 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
(9) 6 A SOFT t 2 2 0 2 1 2 0 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC10 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
| +----------- LC4 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
| | +--------- LC5 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
| | | +------- LC6 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
| | | | +----- LC3 CO8
| | | | | +--- LC1 S86
| | | | | | +- LC2 S87
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B | Logic cells that feed LAB 'A':
LC10 -> - - - * - - - | * - | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
LC4 -> - - - - * - - | * - | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
LC5 -> - - - - * * * | * - | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
LC6 -> - - - - * - * | * - | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
Pin
31 -> * * * - - - - | * * | <-- A84
7 -> * * * - - - - | * * | <-- A85
11 -> * * * - - - - | * - | <-- A86
12 -> - * - * - - - | * - | <-- A87
33 -> * * * - - - - | * * | <-- B84
38 -> * * * - - - - | * * | <-- B85
17 -> * * * - - - - | * - | <-- B86
16 -> - * - * - - - | * - | <-- B87
LC20 -> - - - - * * * | * * | <-- |adder4b:U1|LPM_ADD_SUB:47|addcore:adder|addcore:adder0|result_node4
LC24 -> - - - - * * * | * * | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
LC30 -> - - - - * * * | * - | <-- |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\adder8b\adder8b.rpt
adder8b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC32 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|gcp2
| +--------------------------- LC31 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|g4
| | +------------------------- LC29 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
| | | +----------------------- LC26 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
| | | | +--------------------- LC28 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node2
| | | | | +------------------- LC27 |adder4b:U1|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node3
| | | | | | +----------------- LC20 |adder4b:U1|LPM_ADD_SUB:47|addcore:adder|addcore:adder0|result_node4
| | | | | | | +--------------- LC24 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node0
| | | | | | | | +------------- LC30 |adder4b:U2|LPM_ADD_SUB:46|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +----------- LC21 S80
| | | | | | | | | | +--------- LC19 S81
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