adder8b.vhd

来自「8位加法器VHDL 8位加法器VHDL 8位加法器VHDL」· VHDL 代码 · 共 54 行

--ADDER8B
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT (C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC);
END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
SIGNAL S5: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL A5,B5: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
A5<='0'&A4;
B5<='0'&B4;
S5<=A5+B5+C4;
S4<=S5(3 DOWNTO 0);
CO4<=S5(4);
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder8b IS
PORT (C8: IN STD_LOGIC;
      A8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      B8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      S8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      CO8: OUT STD_LOGIC);
END ENTITY adder8b;


ARCHITECTURE ART OF adder8b IS
COMPONENT adder4b IS
PORT(C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC);
END COMPONENT adder4b;
SIGNAL SC: STD_LOGIC;
BEGIN
U1:ADDER4B
PORT MAP(C4=>C8,A4=>A8 (3 DOWNTO 0),B4=>B8 (3 DOWNTO 0),
S4=>S8(3 DOWNTO 0),CO4=>SC);
U2:ADDER4B
PORT MAP(C4=>SC,A4=>A8 (7 DOWNTO 4),B4=>B8 (7 DOWNTO 4),
S4=>S8 (7 DOWNTO 4),CO4=>CO8);
END ARCHITECTURE ART;