📄 dma4.c
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/* sync == 0 */
/* */
/* DMACICR blockie == 0 */
/* lastie == 0 */
/* frameie == 1 */
/* firsthalfie == 0 */
/* dropie == 0 */
/* timeoutie == 0 */
DMA_Config dmaXmtConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAM,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF,
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_BLOCKIE_OFF,
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON,
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)&xmt[1], /* DMACSSAL */
0, /* DMACSSAU */
(DMA_AdrPtr)(MCBSP_ADDR(DXR11)), /* DMACDSAL */
0, /* DMACDSAU */
N, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
/* Define a DMA_Handle object to be used with DMA_open function */
DMA_Handle hDmaRcv, hDmaXmt;
/* Define a MCBSP_Handle object to be used with MCBSP_open function */
MCBSP_Handle hMcbsp;
/* Protoype for interrupt functions */
interrupt void dmaXmtIsr(void);
interrupt void dmaRcvIsr(void);
void taskFxn(void);
volatile Uint16 transferComplete = FALSE;
Uint16 err = 0;
Uint16 old_intm;
Uint16 xmtEventId, rcvEventId;
/* Main function */
void main(void)
{
Uint16 i;
/* Initialize CSL library - This is REQUIRED !!! */
CSL_init();
/* Set IVPD/IVPH to start of interrupt vector table */
IRQ_setVecs((Uint32)(&VECSTART));
for (i = 0; i <= N - 1; i++) {
xmt[i] = i + 1;
rcv[i] = 0;
}
/* Call function to effect transfer */
taskFxn();
}
void taskFxn(void)
{
Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
Uint16 i;
/* By default, the TMS320C55xx compiler assigns all data symbols word */
/* addresses. The DMA however, expects all addresses to be byte */
/* addresses. Therefore, we must shift the address by 2 in order to */
/* change the word address to a byte address for the DMA transfer. */
srcAddrHi = (Uint16)(((Uint32)(dmaRcvConfig.dmacssal)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(dmaRcvConfig.dmacssal)) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(dmaRcvConfig.dmacdsal)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(dmaRcvConfig.dmacdsal)) << 1) & 0xFFFFu;
dmaRcvConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaRcvConfig.dmacssau = srcAddrHi;
dmaRcvConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacdsau = dstAddrHi;
srcAddrHi = (Uint16)(((Uint32)(dmaXmtConfig.dmacssal)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(dmaXmtConfig.dmacssal)) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(dmaXmtConfig.dmacdsal)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(dmaXmtConfig.dmacdsal)) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
dmaXmtConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaXmtConfig.dmacdsau = dstAddrHi;
/* Open MCBSP Port 1 and set registers to their power on defaults */
hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
/* Open DMA channels 4 & 5 and set regs to power on defaults */
hDmaRcv = DMA_open(DMA_CHA4,DMA_OPEN_RESET);
hDmaXmt = DMA_open(DMA_CHA5,DMA_OPEN_RESET);
/* Get interrupt event associated with DMA receive and transmit */
xmtEventId = DMA_getEventId(hDmaXmt);
rcvEventId = DMA_getEventId(hDmaRcv);
/* Temporarily disable interrupts and clear any pending */
/* interrupts for MCBSP transmit */
old_intm = IRQ_globalDisable();
/* Clear any pending interrupts for DMA channels */
IRQ_clear(xmtEventId);
IRQ_clear(rcvEventId);
/* Enable DMA interrupt in IER register */
IRQ_enable(xmtEventId);
IRQ_enable(rcvEventId);
/* Set Start Of Interrupt Vector Table */
IRQ_setVecs(0x10000);
/* Place DMA interrupt service addresses at associate vector */
IRQ_plug(xmtEventId,&dmaXmtIsr);
IRQ_plug(rcvEventId,&dmaRcvIsr);
/* Write values from configuration structure to MCBSP control regs */
MCBSP_config(hMcbsp, &ConfigLoopBack16);
/* Write values from configuration structure to DMA control regs */
DMA_config(hDmaRcv,&dmaRcvConfig);
DMA_config(hDmaXmt,&dmaXmtConfig);
/* Take MCBSP transmit and receive out of reset */
MCBSP_start(hMcbsp,
MCBSP_XMIT_START | MCBSP_RCV_START,
0u);
/* Prime MCBSP DXR */
while (!(MCBSP_xrdy(hMcbsp))){
;
}
MCBSP_write16(hMcbsp,xmt[0]);
/* Enable all maskable interrupts */
IRQ_globalEnable();
/* Enable DMA */
DMA_start(hDmaRcv);
DMA_start(hDmaXmt);
/* Start Sample Rate Generator and Enable Frame Sync */
MCBSP_start(hMcbsp,
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
0x300u);
/* Wait for DMA transfer to be complete */
while (!transferComplete){
;
}
/*------------------------------------------*\
* Compare values
\*------------------------------------------*/
for(i = 0; i <= N - 1; i++){
if (rcv[i] != xmt[i]){
++err;
break;
}
}
if (err) {
printf(" :-< DMA Example 4 Failed >-:\n");
}
else {
printf(" :-> DMA Example 4 Successful <-:\n");
}
/* Restore status of global interrupt enable flag */
IRQ_globalRestore(old_intm);
/* We're done with MCBSP and DMA , so close them */
MCBSP_close(hMcbsp);
DMA_close(hDmaRcv);
DMA_close(hDmaXmt);
}
interrupt void dmaXmtIsr(void) {
DMA_stop(hDmaXmt);
IRQ_disable(xmtEventId);
}
interrupt void dmaRcvIsr(void) {
DMA_stop(hDmaRcv);
IRQ_disable(rcvEventId);
transferComplete = TRUE;
}
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