📄 m42800.h
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//*--------------------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*--------------------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*--------------------------------------------------------------------------------------
//* File Name : m42800.h
//* Object : AT91M42800 Architecture Definition File
//*
//* 1.0 01/04/00 PFi : Creation
//* 1.1 18/02/02 PFi : #define ST_BASE ((StructST *) 0xFFFF8000) has been added.
//*--------------------------------------------------------------------------------------
#ifndef m42800_h
#define m42800_h
/*-------------------------------------*/
/* Peripheral and Interrupt Identifier */
/*-------------------------------------*/
#define FIQ_ID 0 /* Fast Interrupt */
#define SW_ID 1 /* Soft Interrupt (generated by the AIC) */
#define US0_ID 2 /* USART Channel 0 */
#define US1_ID 3 /* USART Channel 1 */
#define SPIA_ID 4 /* SPI Channel A */
#define SPIB_ID 5 /* SPI Channel B */
#define TC0_ID 6 /* Timer Channel 0 */
#define TC1_ID 7 /* Timer Channel 1 */
#define TC2_ID 8 /* Timer Channel 2 */
#define TC3_ID 9 /* Timer Channel 3 */
#define TC4_ID 10 /* Timer Channel 4 */
#define TC5_ID 11 /* Timer Channel 5 */
#define ST_ID 12 /* System Timer */
#define PIOA_ID 13 /* Parallel I/O Controller A */
#define PIOB_ID 14 /* Parallel I/O Controller B */
#define PMC_ID 15 /* Power Management Controller Interrupt */
#define IRQ3_ID 28 /* External interrupt 3 */
#define IRQ2_ID 29 /* External interrupt 2 */
#define IRQ1_ID 30 /* External interrupt 1 */
#define IRQ0_ID 31 /* External interrupt 0 */
/*-----------------------*/
/* Peripheral Memory Map */
/*-----------------------*/
#define PIOB_BASE ((StructPIO *) 0xFFFF0000) /* Parallel I/O Controller B */
#define PIOA_BASE ((StructPIO *) 0xFFFEC000) /* Parallel I/O Controller A */
#define TCB0_BASE ((StructTCBlock *)0xFFFD0000) /* Channels 0, 1, 2 */
#define TCB1_BASE ((StructTCBlock *)0xFFFD4000) /* Channels 3, 4, 5 */
#define USART1_BASE ((StructUSART *)0xFFFC4000) /* USART 1 */
#define USART0_BASE ((StructUSART *)0xFFFC0000) /* USART 0 */
#define SPIA_BASE ((StructSPI *) 0xFFFC8000) /* SPI A */
#define SPIB_BASE ((StructSPI *) 0xFFFCC000) /* SPI A */
#define ST_BASE ((StructST *) 0xFFFF8000) /* ST: System Timer */
/*-------------------------*/
/* Internal RAM Definition */
/*-------------------------*/
#define RAM_SIZE (8*1024)
#define RAM_BASE ((u_int *)0x00000000)
#define RAM_LIMIT (((u_int)RAM_BASE) + RAM_SIZE)
/* The internal RAM is mapped at address 0x00300000 after reset until
Remap command is performed on the EBI. */
#define RAM_BASE_BOOT ((u_int *)0x00300000)
/*----------*/
/* ARM Core */
/*----------*/
#include "periph/arm7tdmi/arm.h"
/*------------------------*/
/* External Bus Interface */
/*------------------------*/
#include "periph/ebi/ebi.h"
/*------------------------------*/
/* Power Management Controller */
/*------------------------------*/
#include "periph/power_saving/pmc42800.h"
/*-------------------------------*/
/* Advanced Interrupt Controller */
/*-------------------------------*/
#include "periph/aic/lib_aic.h"
/*-------------------------*/
/* Parallel I/O Controller */
/*-------------------------*/
#include "periph/pio/pioa.h"
#include "periph/pio/piob.h"
#include "periph/pio/lib_pio.h"
#define NB_PIOA 30 /* Number of PIO A Lines */
#define NB_PIOB 24 /* Number of PIO B Lines */
/*------------------*/
/* Pin Multiplexing */
/*------------------*/
/* PIO Controller A */
#define PIOIRQ0 0 /* External Interrupt 0 */
#define PIOIRQ1 1 /* External Interrupt 1 */
#define PIOIRQ2 2 /* External Interrupt 2 */
#define PIOIRQ3 3 /* External Interrupt 3 */
#define PIOFIQ 4 /* Fast Interrupt */
#define PIOSCK0 5 /* USART 0 signal */
#define PIOTXD0 6 /* USART 0 transmit data */
#define PIORXD0 7 /* USART 0 receive data */
#define PIOSCK1 8 /* USART 1 clock signal */
#define PIOTXD1 9 /* USART 1 transmit data */
#define PIORXD1 10 /* USART 1 receive data */
#define PIOSPCKA 11 /* SPI A clock signal */
#define PIOMISOA 12 /* SPI A Master In Slave */
#define PIOMOSIA 13 /* SPI A Master Out Slave */
#define PIONPCSA0 14 /* SPI A Peripheral Chip Select 0 */
#define PIONSSA PIONPCSA0
#define PIONPCSA1 15 /* SPI A Peripheral Chip Select 1 */
#define PIONPCSA2 16 /* SPI A Peripheral Chip Select 2 */
#define PIONPCSA3 17 /* SPI A Peripheral Chip Select 3 */
#define PIOSPCKB 18 /* SPI B clock signal */
#define PIOMISOB 19 /* SPI B Master In Slave */
#define PIOMOSIB 20 /* SPI B Master Out Slave */
#define PIONPCSB0 21 /* SPI B Peripheral Chip Select 0 */
#define PIONSSB PIONPCSB0
#define PIONPCSB1 22 /* SPI B Peripheral Chip Select 1 */
#define PIONPCSB2 23 /* SPI B Peripheral Chip Select 2 */
#define PIONPCSB3 24 /* SPI B Peripheral Chip Select 3 */
#define PIOMCKO 25 /* Master Clock Output */
#define PIOBMS 27 /* Boot Mode Select */
#define PIOHOLDA 28 /* Bus Grant to External Device */
#define PIOHOLD 29 /* Bus Request from External Device */
/*------------------*/
/* PIO Controller B */
/*------------------*/
#define PIONCS2 0 /* Chip Select 2 */
#define PIONCS3 1 /* Chip Select 3 */
#define PIOCS7 2 /* Address 20/Chip Select 7 */
#define PIOCS6 3 /* Address 21/Chip Select 6 */
#define PIOCS5 4 /* Address 22/Chip Select 5 */
#define PIOCS4 5 /* Address 23/Chip Select 4 */
#define PIOTCLK0 6 /* Timer 0 Clock signal input */
#define PIOTIOA0 7 /* Timer 0 Signal A */
#define PIOTIOB0 8 /* Timer 0 Signal B */
#define PIOTCLK1 9 /* Timer 1 Clock signal */
#define PIOTIOA1 10 /* Timer 1 Signal A */
#define PIOTIOB1 11 /* Timer 1 Signal B */
#define PIOTCLK2 12 /* Timer 2 Clock signal */
#define PIOTIOA2 13 /* Timer 2 Signal A */
#define PIOTIOB2 14 /* Timer 2 Signal B */
#define PIOTCLK3 15 /* Timer 3 Clock signal */
#define PIOTIOA3 16 /* Timer 3 Signal A */
#define PIOTIOB3 17 /* Timer 3 Signal B */
#define PIOTCLK4 18 /* Timer 4 Clock signal */
#define PIOTIOA4 19 /* Timer 4 Signal A */
#define PIOTIOB4 20 /* Timer 4 Signal B */
#define PIOTCLK5 21 /* Timer 5 Clock signal */
#define PIOTIOA5 22 /* Timer 5 Signal A */
#define PIOTIOB5 23 /* Timer 5 Signal B */
/*---------*/
/* USARTs */
/*---------*/
/* Definition file */
#include "periph/usart/lib_usart.h"
/*--------------*/
/* System Timer */
/*--------------*/
/* Definition file */
#include "periph/system_timer/lib_st.h"
/*---------------*/
/* Timer Counter */
/*---------------*/
#include "periph/timer_counter/lib_tc.h"
#endif /* m42800_h */
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