m63200.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : m63200.h
//* Object              : AT91M63200 Architecture Definition File
//*
//* 1.0 01/04/00 JCZ    : Creation
//*----------------------------------------------------------------------------

#ifndef m63200_h
#define m63200_h

/*-------------------------------------*/
/* Peripheral and Interrupt Identifier */
/*-------------------------------------*/

#define FIQ_ID      0       /* Fast Interrupt */
#define SWIRQ_ID    1       /* Soft Interrupt (generated by the AIC) */
#define US0_ID      2       /* USART Channel 0 */
#define US1_ID      3       /* USART Channel 1 */
#define US2_ID      4       /* USART Channel 2 */
#define SPI_ID      5       /* SPI */
#define TC0_ID      6       /* Timer Channel 0 */
#define TC1_ID      7       /* Timer Channel 1 */
#define TC2_ID      8       /* Timer Channel 2 */
#define TC3_ID      9       /* Timer Channel 3 */
#define TC4_ID      10      /* Timer Channel 4 */
#define TC5_ID      11      /* Timer Channel 5 */
#define WD_ID       12      /* Watchdog */
#define PIOA_ID     13      /* Parallel I/O Controller A */
#define PIOB_ID     14      /* Parallel I/O Controller B */

#define IRQ3_ID     28      /* External interrupt 3 */
#define IRQ2_ID     29      /* External interrupt 2 */
#define IRQ1_ID     30      /* External interrupt 1 */
#define IRQ0_ID     31      /* External interrupt 0 */

/*-----------------------*/
/* Peripheral Memory Map */
/*-----------------------*/

#define WD_BASE         (( StructWD *) 0xFFFF8000)      /* WD: Watchdog Timer */
#define PIOB_BASE       ((StructPIO *) 0xFFFF0000)      /* Parallel I/O Controller B */
#define PIOA_BASE       ((StructPIO *) 0xFFFEC000)      /* Parallel I/O Controller A */
#define TCB1_BASE       ((StructTCBlock *)0xFFFD4000)   /* Channels 3, 4, 5 */
#define TCB0_BASE       ((StructTCBlock *)0xFFFD0000)   /* Channels 0, 1, 2 */
#define USART2_BASE     ((StructUSART*)0xFFFC8000)      /* USART 2 */
#define USART1_BASE     ((StructUSART*)0xFFFC4000)      /* USART 1 */
#define USART0_BASE     ((StructUSART*)0xFFFC0000)      /* USART 0 */
#define SPI_BASE        ((StructSPI *) 0xFFFBC000)      /* SPI */

/*-------------------------*/
/* Internal RAM Definition */
/*-------------------------*/

#define RAM_SIZE        (2*1024)
#define RAM_BASE        ((u_int *)0x00000000)
#define RAM_LIMIT       (((u_int)RAM_BASE) + RAM_SIZE)

/* The internal RAM is mapped at address 0x00300000 after reset until
   Remap command is performed on the EBI. */

#define RAM_BASE_BOOT       ((u_int *)0x00300000)

#define MPI_BASE            0x00400000

/*----------*/
/* ARM Core */
/*----------*/
#include    "periph/arm7tdmi/arm.h"

/*----------------------------*/
/* Special Function Registers */
/*----------------------------*/
#include    "periph/special_function/sf.h"

/*------------------------*/
/* External Bus Interface */
/*------------------------*/
#include    "periph/ebi/ebi.h"

/*------------------------------*/
/* Power Management Controller  */
/*------------------------------*/
#include    "periph/power_saving/pmc63200.h"

/*-------------------------------*/
/* Advanced Interrupt Controller */
/*-------------------------------*/
#include    "periph/aic/lib_aic.h"

/*-------------------------*/
/* Parallel I/O Controller */
/*-------------------------*/
#include    "periph/pio/pioa.h"
#include    "periph/pio/piob.h"
#include    "periph/pio/lib_pio.h"

#define NB_PIOA         30          /* Number of PIO A Lines */
#define NB_PIOB         28          /* Number of PIO A Lines */

/*------------------*/
/* Pin Multiplexing */
/*------------------*/
/* PIO Controller A */
#define PIOTCLK3        0         /* Timer 3 Clock signal */
#define PIOTIOA3        1         /* Timer 3 Signal A */
#define PIOTIOB3        2         /* Timer 3 Signal B */
                                   
#define PIOTCLK4        3         /* Timer 4 Clock signal */
#define PIOTIOA4        4         /* Timer 4 Signal A */
#define PIOTIOB4        5         /* Timer 4 Signal B */
                                   
#define PIOTCLK5        6         /* Timer 5 Clock signal */
#define PIOTIOA5        7         /* Timer 5 Signal A */
#define PIOTIOB5        8         /* Timer 5 Signal B */
                                    
#define PIOIRQ0         9         /* External Interrupt 0 */
#define PIOIRQ1         10        /* External Interrupt 1 */
#define PIOIRQ2         11        /* External Interrupt 2 */
#define PIOIRQ3         12        /* External Interrupt 3 */
#define PIOFIQ          13        /* Fast Interrupt */
                                   
#define PIOSCK0         14        /* USART 0 signal */
#define PIOTXD0         15        /* USART 0 transmit data */
#define PIORXD0         16        /* USART 0 receive data  */
                                  
#define PIOSCK1         17        /* USART 1 clock signal  */
#define PIOTXD1         18        /* USART 1 transmit data */
#define PIORXD1         19        /* USART 1 receive data  */
                                   
#define PIOSCK2         20        /* USART 2 clock signal   */
#define PIOTXD2         21        /* USART 2 transmit data  */
#define PIORXD2         22        /* USART 2 receive data   */
                                   
#define PIOSPCK         23        /* SPI clock signal */ 
#define PIOMISO         24        /* SPI Master In Slave */
#define PIOMOSI         25        /* SPI Master Out Slave */
#define PIONPCS0        26        /* SPI Peripheral Chip Select 0 */
#define PIONSS          PIONPCS0    
#define PIONPCS1        27        /* SPI Peripheral Chip Select 1 */
#define PIONPCS2        28        /* SPI Peripheral Chip Select 2 */
#define PIONPCS3        29        /* SPI Peripheral Chip Select 3 */

/* PIO Controller B */
#define PIOTCLK0        19        /* Timer 0 Clock signal input */
#define PIOTIOA0        20        /* Timer 0 Signal A   */
#define PIOTIOB0        21        /* Timer 0 Signal B   */
                                   
#define PIOTCLK1        22        /* Timer 1 Clock signal */
#define PIOTIOA1        23        /* Timer 1 Signal A */
#define PIOTIOB1        24        /* Timer 1 Signal B */
                                       
#define PIOTCLK2        25        /* Timer 2 Clock signal */
#define PIOTIOA2        26        /* Timer 2 Signal A */
#define PIOTIOB2        27        /* Timer 2 Signal B */
                                     
#define PIOMCKO         17        /* Master Clock Output */
                                  
#define PIOBMS          18        /* Boot Mode Select */
                                  
#define PIOMPI_NOE      0         /* MPI output enable */
#define PIOMPI_NLB      1         /* MPI lower byte select */
#define PIOMPI_NUB      2         /* MPI upper byte select */
                                                          
                                  
/*--------*/                      
/* USARTs */                      
/*--------*/                      
/* Definition file */             
#include    "periph/usart/lib_usart.h"
                                  
/*----------*/                    
/* Watchdog */
/*----------*/
/* Definition file */
#include    "periph/watchdog/lib_wd.h"

/*---------------*/
/* Timer Counter */
/*---------------*/
#include    "periph/timer_counter/lib_tc.h"


#endif /* m63200_h */