📄 cstartup.paf.arm
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#define IRQ_STACK_SIZE (3*8*4)
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#define FIQ_STACK_SIZE (3*4)
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#define ABT_STACK_SIZE (1*4)
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#define UND_STACK_SIZE (1*4)
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#define TOP_EXCEPTION_STACK RAM_LIMIT
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#define TOP_APPLICATION_STACK EXT_SRAM_LIMIT
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ldr r0, =TOP_EXCEPTION_STACK
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msr CPSR_c, ARM_MODE_FIQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, FIQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, IRQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_ABORT | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, ABT_STACK_SIZE
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msr CPSR_c, ARM_MODE_UNDEF | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, UND_STACK_SIZE
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msr CPSR_c, ARM_MODE_SVC | I_BIT | F_BIT
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mov r13, r0
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msr CPSR_c, ARM_MODE_USER
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ldr r13, =TOP_APPLICATION_STACK
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.weak __ghsbegin_bss
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.weak __ghsend_bss
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ldr r1, =__ghsend_bss
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ldr r3, =__ghsbegin_bss
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mov r2, 0
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LoopZI
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cmp r3, r1
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strcc r2, [r3], 4
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bcc LoopZI
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.weak __ghsbegin_sbss
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.weak __ghsend_sbss
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ldr r1, =__ghsend_sbss
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ldr r3, =__ghsbegin_sbss
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mov r2, 0
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LoopZI2
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cmp r3, r1
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strcc r2, [r3], 4
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bcc LoopZI2
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.weak __ghsbegin_data
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.weak __ghsend_data
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.weak __ghsbegin_romdata
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ldr r0, =__ghsbegin_romdata
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ldr r1, =__ghsbegin_data
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ldr r3, =__ghsend_data
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LoopRW
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cmp r1, r3
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ldrcc r2, [r0], 4
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strcc r2, [r1], 4
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bcc LoopRW
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IMPORT main
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ldr r0, =main
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mov lr, pc
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bx r0
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End
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b End
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.type __main, $function
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.size __main,.-__main
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/*END*/
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__low_level_init
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#if defined(SRAM_TEST_ENABLE )
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mov r0, 0
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ldr r1, =0x00040000
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mov r2, r0
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mvn r3, r0
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mov r4, r0
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mov r5, r0
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mov r6, r0
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w0_loop0_pass1
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cmp r6, r1
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beq r0_loop1_pass1
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str r2, [r6]
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add r6, r6,4
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b w0_loop0_pass1
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r0_loop1_pass1
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sub r6, r1,4
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sub r7, r0,4
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r0_loop_1_pass1
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cmp r6, r7
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beq r1_loop2_pass1
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop1_pass1
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add r4, r4,1
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w1_loop1_pass1
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str r3, [r6]
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sub r6, r6,4
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b r0_loop_1_pass1
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r1_loop2_pass1
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mov r6, r0
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r1_loop_pass1
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cmp r6, r1
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beq r1_w0_loop3_pass1
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop2_pass1
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add r4, r4,1
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w0_loop2_pass1
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str r2, [r6]
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop2_pass1
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add r4, r4,1
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w1_loop2_pass1
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str r3, [r6]
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add r6, r6,4
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b r1_loop_pass1
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r1_w0_loop3_pass1
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mov r6, r0
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r1_loop3_pass1
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cmp r6, r1
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beq r0_w1_r1_w0_loop4_pass1
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop3_pass1
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add r4, r4,1
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w0_loop3_pass1
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str r2, [r6]
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add r6, r6,4
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b r1_loop3_pass1
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r0_w1_r1_w0_loop4_pass1
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mov r6, r0
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r0_loop4_pass1
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cmp r6, r1
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beq r0_loop5_pass1
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop4_pass1
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add r4,r4,1
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w1_loop4_pass1
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str r3, [r6]
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r1_loop4_pass1
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop4_pass1
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add r4, r4,1
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w0_loop4_pass1
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str r2, [r6]
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add r6, r6,4
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b r0_loop4_pass1
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r0_loop5_pass1
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mov r6, r0
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r0_loop_pass1
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cmp r6, r1
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beq write_result_pass1
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ldr r5, [r6]
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add r6, r6,4
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cmp r5, r2
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beq r0_loop_pass1
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add r4, r4,1
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b r0_loop_pass1
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write_result_pass1
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cmp r4, 0
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bne test_failed_pass1
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ldr r0,=0x0000BEAD
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ldr r1,=0x20000
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str r0,[r1]
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b march_lr_end_pass1
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test_failed_pass1
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ldr r0,=0x00000BAD
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ldr r1,=0x20000
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str r0,[r1]
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march_lr_end_pass1
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mov r0, 0
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ldr r1, =0x00040000
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ldr r2, =0x55555555
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mvn r3, r2
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mov r4, r0
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mov r5, r0
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mov r6, r0
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w0_loop0_pass2
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cmp r6, r1
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beq r0_loop1_pass2
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str r2, [r6]
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add r6, r6,4
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b w0_loop0_pass2
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r0_loop1_pass2
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sub r6, r1,4
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sub r7, r0,4
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r0_loop_1_pass2
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cmp r6, r7
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beq r1_loop2_pass2
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop1_pass2
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add r4, r4,1
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w1_loop1_pass2
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str r3, [r6]
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sub r6, r6,4
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b r0_loop_1_pass2
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r1_loop2_pass2
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mov r6, r0
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r1_loop_pass2
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cmp r6, r1
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beq r1_w0_loop3_pass2
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop2_pass2
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add r4, r4,1
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w0_loop2_pass2
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str r2, [r6]
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop2_pass2
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add r4, r4,1
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w1_loop2_pass2
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str r3, [r6]
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add r6, r6,4
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b r1_loop_pass2
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r1_w0_loop3_pass2
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mov r6, r0
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r1_loop3_pass2
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cmp r6, r1
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beq r0_w1_r1_w0_loop4_pass2
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop3_pass2
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add r4, r4,1
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w0_loop3_pass2
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str r2, [r6]
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add r6, r6,4
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b r1_loop3_pass2
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r0_w1_r1_w0_loop4_pass2
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mov r6, r0
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r0_loop4_pass2
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cmp r6, r1
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beq r0_loop5_pass2
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ldr r5, [r6]
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cmp r5, r2
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beq w1_loop4_pass2
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add r4,r4,1
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w1_loop4_pass2
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str r3, [r6]
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r1_loop4_pass2
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ldr r5, [r6]
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cmp r5, r3
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beq w0_loop4_pass2
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add r4, r4,1
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w0_loop4_pass2
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str r2, [r6]
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add r6, r6,4
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b r0_loop4_pass2
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r0_loop5_pass2
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mov r6, r0
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r0_loop_pass2
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cmp r6, r1
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beq write_result_pass2
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ldr r5, [r6]
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add r6, r6,4
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cmp r5, r2
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beq r0_loop_pass2
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add r4, r4,1
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b r0_loop_pass2
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write_result_pass2
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cmp r4, 0
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bne test_failed_pass2
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ldr r0,=0x0000BEAD
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ldr r1,=0x20004
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str r0,[r1]
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b march_lr_end_pass2
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test_failed_pass2
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ldr r0,=0x00000BAD
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ldr r1,=0x20004
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str r0,[r1]
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march_lr_end_pass2
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#endif
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mov pc,r14
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#endif
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/*END*/
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