📄 cstartup_angel.arm
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : cstartup_angel.arm
;- Object : Specific Startup for Angel compatibility
;- : Must be loaded in SRAM
;- : Support the Semihosting
;- Compilation flag : SEMIHOSTING => use the semihosting facilities
;-
;- 1.0 05/11/00 EL : Creation Green Hills
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at SRAM.
;------------------------------------------------------------------------------
AREA reset, CODE, READONLY, INTERWORK
;------------------------------------------------------------------------------
;- Semihosting support
;--------------------------------
;- The C runtime library is the IO functions provided by the semihosting.
;- They are generally costly in code and can be used as the debugger
;------------------------------------------------------------------------------
;- Define "__main" to ensure that C runtime system is not linked
EXPORT __main
__main
;------------------------------------------------------------------------------
;- Exception vectors ( Remap is managed by Angel )
;------------------------------------------------------------------------------
B InitReset ; reset
;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------
;- The EBI User Interface Image which is copied by the boot.
;- The EBI_CSR_x are defined in the target and hardware depend.
;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
;- EBI Base Address is added at the end for commodity in copy code.
;------------------------------------------------------------------------------
InitTableEBI
DCD EBI_CSR_0
DCD EBI_CSR_1
DCD EBI_CSR_2
DCD EBI_CSR_3
DCD EBI_CSR_4
DCD EBI_CSR_5
DCD EBI_CSR_6
DCD EBI_CSR_7
DCD 0x00000001 ; REMAP command
DCD 0x00000006 ; 6 memory regions, standard read
PtEBIBase
DCD EBI_BASE ; EBI Base Address
;------------------------------------------------------------------------------
;- The reset handler before Remap
;--------------------------------
;- From here, the code is executed from SRAM address
;------------------------------------------------------------------------------
InitReset
;----------------------------------------------------------------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
;----------------------------------------------------------------------
bl __low_level_init
;------------------------------------------------------------------------------
;- Initialise the Memory Controller
;----------------------------------
;- The IniTableEBI addressing must be relative .
;- The PtInitRemap must be absolute as the processor jumps at this address
;- Note also that the EBI base address is loaded in r11 by the "ldmia".
;------------------------------------------------------------------------------
;- Copy the Image of the Memory Controller
sub r10, pc,8+.-InitTableEBI ; get the address of the chip select register image
;- Copy Chip Select Register Image to Memory Controller and command remap
ldmia r10!, {r0-r9,r11} ; load the complete image and the EBI base
stmia r11!, {r0-r9} ; store the complete image with the remap command
;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 3 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt is the same than Interrupt without priority level.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------
IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per interrupt priority level
FIQ_STACK_SIZE EQU (3*4) ; 3 words
ABT_STACK_SIZE EQU (1*4) ; 1 word
UND_STACK_SIZE EQU (1*4) ; 1 word
;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Fast Interrupt, Interrupt, Abort, Undefined and Supervisor Stack are located
;- at the top of internal memory in order to speed the exception handling
;- context saving and restoring.
;- User (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
TOP_EXCEPTION_STACK EQU RAM_LIMIT ; Defined in part
TOP_APPLICATION_STACK EQU EXT_SRAM_LIMIT ; Defined in Target
;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
ldr r0, =TOP_EXCEPTION_STACK
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Abort
sub r0, r0, #ABT_STACK_SIZE
;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Undef
sub r0, r0, #UND_STACK_SIZE
;- Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Sup
;------------------------------------------------------------------------------
;- Setup Application Operating Mode and Enable the interrupts
;------------------------------------------------------------
;- System Mode is selected first and the stack is setup. This allows to prevent
;- any interrupt occurence while the User is not initialized. System Mode is
;- used as the interrupt enabling would be avoided from User Mode (CPSR cannot
;- be written while the core is in User Mode).
;------------------------------------------------------------------------------
msr CPSR_c, #ARM_MODE_USER ; set User mode
ldr r13, =TOP_APPLICATION_STACK ; Init stack User
;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------------------------------------------------------------
.weak __ghsbegin_bss
.weak __ghsend_bss
ldr r1, =__ghsend_bss ; Get pointer to top of BSS
ldr r3, =__ghsbegin_bss ; Bottom of BSS
mov r2, 0
LoopZI
cmp r3, r1
strcc r2, [r3], 4
bcc LoopZI
;- Clear SBSS (zero init)
;- ----------------------
.weak __ghsbegin_sbss
.weak __ghsend_sbss
ldr r1, =__ghsend_sbss ; Get pointer to top of SBSS
ldr r3, =__ghsbegin_sbss ; Bottom of SBSS
mov r2, 0
LoopZI2
cmp r3, r1
strcc r2, [r3], 4
bcc LoopZI2
IF :DEF:SEMIHOSTING
;- Branch on Entry point
;- ---------------------
;- Allows semihosting initialisation
SEMIHOSTING_STACK_SIZE EQU (8*1024) ;
ldr r0, = SEMIHOSTING_STACK_SIZE
sub r13, r13,r0
.weak __ghsbegin_robase
mov fp, 0 ; No previous frame
ldr r0, pool_baseptrs ; Could use add r0, pc, offset
bl __ghs_ind_crt0 ; Go to C land
pool_baseptrs:
.data.w baseptrs
baseptrs:
.data.w __ghsbegin_picbase
.data.w __ghsbegin_robase
.data.w __ghsbegin_pidbase
ELSE ; not use SEMIHOSTING
;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors
;------------------------------------------------------------------------------
IMPORT main
ldr r0, =main
mov lr, pc
bx r0
ENDIF ; endif SEMIHOSTING
;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
b End
.type __main, $function
.size __main,.-__main
END
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