except.s

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

        TTL     Angel exception support                 > except.s
        ;
        ; This file provides the default Angel exception vector handlers.
        ;
        ; $Revision: 1.16.4.4 $
        ;   $Author: dbrooke $
        ;     $Date: 1998/02/26 17:35:12 $
        ;
        ; Copyright Advanced RISC Machines Limited, 1995.
        ; All Rights Reserved
        ;

        KEEP

        GET     listopts.s           ; standard listing control
        GET     lolevel.s            ; automatically built manifest definitions
        GET     macros.s             ; standard assembler support
        GET     target.s             ; target specific manifests


        EXPORT  __VectorStart
        EXPORT  __SoftVectors
	EXPORT  DefaultExceptionTable
        IMPORT  angel_DeviceInterruptHandler
   IF :DEF: AT91_AIC_IRQ
     IF AT91_AIC_IRQ = 2
	IMPORT Interrupt_veneer	             
     ENDIF	
   ENDIF

	
        ;
        ; Default ARM hardware exception vectors
        ;
        ; When building ROM at zero systems, the link should be modified
        ; to force this area to be first.
        IF      ROMonly
          AREA    |__Vectors|,CODE,PIC,READONLY
        ELSE
          ; Masquerade as ReadWrite Code so that this AREA gets placed first
          ; in the Read-Write segment by the linker, and has two underscores
          ; to help it get sorted first in case anyone has any real RW Code !
          AREA    |__Vectors|,CODE,PIC,READWRITE
        ENDIF
        ;
        ; After initialisation the following vectors *MUST* start at
        ; 0x00000000 (an ARM processor requirement).
        ;
        ; The following vectors load the address of the relevent
        ; exception handler from an address table.  This makes it
        ; possible for these handlers to be anywhere in the address space.
        ;
        ; To bootstrap the ARM, some form of ROM is present at
        ; 0x00000000 during reset.  Often the startup code performs
        ; some target specific magic to remap RAM to address
        ; zero. The ROM based Read/Write data and BSS must then be
        ; copied to the relevant RAM address during the Angel ROM
        ; initialisation.
        ;
__VectorStart                   ; Start of ARM processor vectors
        LDR     pc,ResetV       ; 00 - Reset
        LDR     pc,UndefV       ; 04 - Undefined instructions
        LDR     pc,SWIV         ; 08 - SWI instructions
        LDR     pc,PAbortV      ; 0C - Instruction fetch aborts
        LDR     pc,DAbortV      ; 10 - Data access aborts
        LDR     pc,UnusedV      ; 14 - Reserved (was address exception)
	;; PLace in INT_AIC If here - dawb
	IF :DEF: AT91_AIC_IRQ
		IF ( AT91_AIC_IRQ =1 )
		LDR	pc,[pc,#-0xF20] ; AIC Controller vector location - FIQ
		ELSE
		LDR     pc,IRQV         ; 18 - FIQ interrupts
		ENDIF
	ELSE
		LDR     pc,IRQV         ; 18 - FIQ interrupts
	ENDIF

	
   IF (:DEF: AT91_AIC_FIQ )
	LDR	pc,[pc,#-0xF20] ; AIC Controller vector location - FIQ
   ELSE
	LDR     pc,FIQV         ; 1C - FIQ interrupts
   ENDIF
	; In this case we are using the ATMEL AT91 Advanced Interrupt
	; Controller (AIC) 	
        ;
        ; NOTE: In a normal optimised ARM system the FIQ vector would
        ; not contain a branch to handler code, but would have an
        ; allocation immediately following address 0x1C, with the FIQ
        ; code being placed directly after the vector table. This
        ; avoids the pipe-line breaks associated with indirecting to a
        ; handler routine.

        ; However Angel is designed to be a simple system so we
        ; treat FIQ like all the other vectors, and this allows the
        ; actual handler addresses to be stored immediately after the
        ; ARM vectors. If optimal FIQ entry is required, then space
        ; could be allocated at this point to hold the direct FIQ
        ; code. The __SoftVectors table would then simply appear
        ; higher in the RAM allocation.
        ;
__SoftVectors
        ; Reset - an error unless ROM always at zero, or a branch
        ; to High ROM on reset has been requested explicitly (Cogent Board)

ResetV  
  IF ROMonly
        IMPORT  __rom
        DCD     __rom           ; 00 - Reset
  ELSE
    IF BRANCH_TO_HIGH_ROM_ON_RESET <> 0
        DCD     ROMBase
    ELSE
        DCD     DefaultExceptionTable + 0x0
    ENDIF
  ENDIF
        
  IF :DEF: ICEMAN_LEVEL_3 :LOR: (:DEF: MINIMAL_ANGEL :LAND: MINIMAL_ANGEL<>0)
UndefV  DCD     DefaultExceptionTable + 0x4
  ELSE
UndefV  DCD     HandlerUndef
  ENDIF
SWIV    DCD     HandlerSWI
PAbortV DCD     DefaultExceptionTable + 0xC
DAbortV DCD     DefaultExceptionTable + 0x10
UnusedV DCD     DefaultExceptionTable + 0x14
	
	IF HANDLE_INTERRUPTS_ON_IRQ <> 0
		IF :DEF: AT91_AIC_IRQ 
			IF  (AT91_AIC_IRQ=2)
IRQV    DCD     Interrupt_veneer
			ELSE
IRQV    DCD     angel_DeviceInterruptHandler	             
			ENDIF	
		ELSE
IRQV    DCD     angel_DeviceInterruptHandler	             
		ENDIF	
	
	ELSE
IRQV    DCD     DefaultExceptionTable + 0x18
	ENDIF
  
  IF HANDLE_INTERRUPTS_ON_FIQ <> 0
FIQV    DCD     angel_DeviceInterruptHandler
  ELSE
FIQV    DCD     DefaultExceptionTable + 0x1C
  ENDIF

        
__VectorEnd             ; End of Angel code copied to zero


        AREA    |ExceptionInit|,CODE,PIC,READONLY

        IMPORT  angelOS_ThreadStopped
        IMPORT  angel_ApplDeviceHandler
        IMPORT  angel_LateBootInit

  IF :LNOT: ROMonly     ;This is removed for FLASH at 0 systems where a 
        ;; write to the flash may cause reprogramming - in the case of the
        ;; ATMEL devices on the PID. If ROM is at 0 there is no need to
        ;; initialise the vectors as they are hard coded.
        
        ; This function performs the exception system initialisation:
        
        EXPORT angel_ExceptionInit
angel_ExceptionInit
        ; in:   no arguments
        ; out:  no result
        ;
        ; Here we copy the vector table (__VectorStart to __VectorEnd)
        ; to address 0.
        ; This is clearly necessary if we have a RAM based system, and
        ; is clearly pointless if we have a ROM at 0 based system.

        LDR     a1,=__VectorStart       ; start of data
        MOV     a2,#0x00000000          ; destination address
        LDR     a3,=__VectorEnd         ; end of data
01      LDR     a4,[a1],#4              ; get word from data AREA
        STR     a4,[a2],#4              ; store to RAM at zero
        CMP     a1,a3                   ; check for end condition
        BLO     %BT01                   ; if (a2 < a3) we have more to transfer
        ;
        MOV     pc,lr

  ENDIF ;:LNOT: ROMonly 
        
        ; *****************************************************************

  IF (:DEF: MINIMAL_ANGEL :LAND: MINIMAL_ANGEL<>0)

        AREA    |MinimalRegBlock|,DATA,NOINIT

        EXPORT  Angel_MutexSharedTempRegBlocks

Angel_MutexSharedTempRegBlocks
        %       (2 + 16) * 4

  ELSE
    IF (:DEF: ICEMAN_LEVEL_3)
        IMPORT  Angel_MutexSharedTempRegBlocks
    ENDIF
  ENDIF
        
        ; Exception handlers

        AREA    |DefaultVectorHandlers|,CODE,PIC,READONLY

        ; This is the ARM exception interface to the Angel debug world.
        ;
        ; This code provides the default ARM vector handlers for the
        ; processor exceptions. If the target application (or the
        ; more likely an O/S) does provide vector handlers,
        ; then they should be coded to provide the VectorCatch
        ; checking code performed below, to ensure that a debug agent
        ; can stop on system events. However, this is very system
        ; specific.
        ;
        ; By default the Angel debug world makes use of the
        ; Undefined Instruction exception, SWI's and eother IRQ's or
        ; FIQ's depending on which the board uses.  All of the
        ; other exceptions are unused by Angel, and the default action
        ; is purely to raise a debug event.
        ;
        ; The model used by the serialisation module is discussed
        ; in detail elsewhere.  This module follows the rules and
        ; guidelines laid out by the serialiser.

        ; in: UND mode; IRQs disabled; FIQs undefined
        ;     r13 = FD stack
        ;     r14 = address of undefined instruction + 4
        ;     All other registers must be preserved

  IF :DEF: ICEMAN_LEVEL_3 :LOR: (:DEF: MINIMAL_ANGEL :LAND: MINIMAL_ANGEL<>0)
        ; Do not include an Undef Handler for ICEMan
  ELSE  
        IMPORT Angel_MutexSharedTempRegBlocks
        EXPORT HandlerUndef 

HandlerUndef
        STMFD sp!, {r0}

        ; Disable interrupts
        MRS   r0, CPSR
        IF (FIQ_SAFETYLEVEL >= \
            FIQ_NeverUsesSerialiser_DoesNotReschedule_HasNoBreakpoints)
          ORR r0, r0, #IRQDisable
        ELSE
          ORR r0, r0, #IRQDisable + FIQDisable
        ENDIF
        MSR   CPSR_cxsf, r0

        ; Save the state of the callee into a regblock
        ; This means r0-r15, cpsr and if appropriate spsr
        ;
        ; Can do r0-r7, pc, cpsr for all modes
        LDR   r0, =Angel_MutexSharedTempRegBlocks
        ADD   r0, r0, #Angel_RegBlock_R0offset + (1*4)
        STMIA r0, {r1-r7}       ; r1-r7 are never banked
        SUB   r0, r0, #Angel_RegBlock_R0offset + (1*4)
        LDMFD sp!, {r1}
        STR   r1, [r0, #Angel_RegBlock_R0offset] ; original r0
        MRS   r1, SPSR
        STR   r1, [r0, #Angel_RegBlock_CPSRoffset] ; original cpsr
        IF :DEF: THUMB_SUPPORT :LAND: THUMB_SUPPORT<>0
          TST   r1, #Tbit
          SUBEQ r14, r14, #4      ; Adjust for ARM instruction
          SUBNE r14, r14, #2      ; Adjust for Thumb instruction
        ELSE
          SUB   r14, r14, #4      ; Adjust to point to the undef
        ENDIF
        STR   r14, [r0, #Angel_RegBlock_R0offset + (15*4)] ; pc

        ; Accessing other modes depends on the mode
        AND   r1, r1, #ModeMask
        CMP   r1, #USRmode
        BEQ   UndefWasInUSRMode
        CMP   r1, #SYSmode
        BEQ   UndefWasInUSRMode

        ; Deal with non USR mode case
        IF (FIQ_SAFETYLEVEL >= \
            FIQ_NeverUsesSerialiser_DoesNotReschedule_HasNoBreakpoints)
          ORR r1, r1, #IRQDisable
        ELSE
          ORR r1, r1, #IRQDisable + FIQDisable
        ENDIF
        MSR   CPSR_cxsf, r1  

        ; Now we are in the appropriate mode
        ADD   r0, r0, #Angel_RegBlock_R0offset + (8*4)
        STMIA r0, {r8-r14}      ; r8-r12 may be banked - now saved
        SUB   r0, r0, #Angel_RegBlock_R0offset + (8*4)
        MRS   r2, SPSR
        STR   r2, [r0, #Angel_RegBlock_SPSRoffset]

        ; Get back into UND
        BIC   r1, r1, #ModeMask
        ORR   r1, r1, #UNDmode
        MSR   CPSR_cxsf, r1
        B     RegsNowSaved

UndefWasInUSRMode
        ADD   r0, r0, #Angel_RegBlock_R0offset + (8*4)
        STMIA r0, {r8-r12}      ; r8-r12 are not banked between USR and UND
        ADD   r0, r0, #(13*4) - (8*4)