startrom.s

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

        ; The value in "r7" is the true ROM end address. This can be
        ; used by ROM systems that have appended data after that
        ; constructed by the linker.

        LDR     r0, =angel_ROMEnd        ; variable to hold true ROM end address
        STR     r7,[r0,#0x00]
        ;
        ; The MMU identification word is held in r6 from above. A
        ; value of zero is used when no MMU is present.
        
        LDR     r0,=angel_MMUtype
        STR     r6,[r0,#0x00]

        ;
        ; We can support the following three system configurations:
        ;
        ; 1)  ROM at zero, (dataseg, bss) elsewhere
        ;
        ; 2)  ROM elsewhere, (dataseg, bss) at zero
        ;
        ; 3)  Vectors at zero, (ROM, dataseg, bss) elsewhere
        ;
        ; In the first two configurations, the Vectors will automatically
        ; be at zero (in (1) because the linker was told to put them there,
        ; in (2) because they are linked at the start of the "dataseg");
        ; in the third configuration we need to copy them from their
        ; current position to their proper home at zero.
        ;
        LDR     r0, =|__Vectors$$Base|
        CMP     r0, #0
        BEQ     VectorsInPlace

        ;
        ; we really do need to move the vectors
        ;
        LDR     r3, =|__Vectors$$Limit|
        SUBS    r3, r3, r0

        IF :DEF: ASSERT_ENABLED :LAND: ASSERT_ENABLED <> 0
MissingVectors
        BNE     VectorsOK
        ADR     a1, novecmsg
        B       __rt_asm_fatalerror
novecmsg
        DCB     "Missing Vectors\n"
        ALIGN
VectorsOK
        ENDIF

        MOV     r1, #0
VectorCopy
        LDR     r2, [r0], #4
        STR     r2, [r1], #4
        SUBS    r3, r3, #4
        BNE     VectorCopy

        ;
        ; We now have the processor vectors, and the indirection table
        ; at address zero. Also, depending on the target, we will have
        ; mapped RAM to zero.
        ;
        ; Initialise the default stack pointers for the various ARM
        ; processor modes. We do this by switching into all the modes
        ; (ensuring interrupts stay disabled), setting up the default
        ; stack top addresses. These addresses are hard-wired into the
        ; target workspace. Normally an O/S would perform some more
        ; memory management, and have the concept of dynamic exception
        ; stacks depending on the task/thread active. However for
        ; Angel we just have some pre-allocated stacks at fixed
        ; addresses in the work-space.
        ;

        IMPORT  Angel_StackBase
VectorsInPlace
;			LDR		r5, =|Image$$RW$$Limit|
;        LDR     r1, =Angel_StackBase
;        STR     r5, [r1]

        LDR     r5, =Angel_StackBase
        LDR     r5, [r5]
        ADD     sp, r5, #Angel_SVCStackOffset      ; SVC mode stack
        ADD     sl, r5, #Angel_SVCStackLimitOffset ; No APCS_STACKGUARD space

        ; Define a default APCS-3 register state to ensure we can call
        ; suitably conforming functions:
        MOV     fp,#0x00000000          ; no frame-pointer chain

        ; We now call the memory sizer if there is one, and adjust
        ; things if the memory size is not the default.

        IMPORT  angel_FindTopOfMemory, WEAK
        IMPORT  angel_RelocateWRTTopOfMemory, WEAK
        
        LDR     r1, =angel_FindTopOfMemory
        CMP     r1, #0
        BEQ     MemorySizeAlreadyCorrect
        BL      angel_FindTopOfMemory
        BL      angel_RelocateWRTTopOfMemory
        ; If we have just done relocations then go back and set up the SVC
        ; stack again (and repeat this).
        CMP     r0, #0
        BNE     VectorsInPlace
        ; Now everything is all ok, and set up correctly
        
MemorySizeAlreadyCorrect        
        ; We have to set up the other privileged mode regs right now.
        
        MOV     r0, #(InterruptMask :OR: IRQmode)
        MSR     CPSR_cxsf,r0
        ADD     sp, r5, #Angel_IRQStackOffset      ; IRQ mode stack

        MOV     r0, #(InterruptMask :OR: FIQmode)
        MSR     CPSR_cxsf,r0
        ADD     sp, r5, #Angel_FIQStackOffset      ; FIQ mode stack

        MOV     r0,#(InterruptMask :OR: UNDmode)
        MSR     CPSR_cxsf,r0
        ADD     sp, r5, #Angel_UNDStackOffset      ; Undefined instruction mode stack

        MOV     r0,#(InterruptMask :OR: SVCmode)
        MSR     CPSR_cxsf,r0

        ; We are now back in SVC mode with IRQs and FIQs disabled.

    IF AT91_AIC_IRQ = 1
   GET		 aic.inc
	 INITAIC		r0,r1,r2,r3 ; Set up the initialisation for the AIC
    ENDIF
	
        INITMMU         r0,r1,r2,r3,r5,r6  ; perform MMU initialisation if required
        ;
        INITTIMER       r0,r1  ; perform any special timer initialisation
        ;
        ; For systems that cannot tell the type of reset that
        ; occurred, the STARTUPCODE macro will have set "r4" to
        ; pretend that it is a PowerOnReset.
        LDR     r0,=angel_StartupStatus
        STR     r4,[r0,#0x00]                   ; store PowerOnReset status

        ; NOTE: At this point we are still in SVC mode, using the
        ; SVC stack. Processor interrupts are *STILL* disabled.

  IF (:LNOT: :DEF: MINIMAL_ANGEL) :LOR: MINIMAL_ANGEL = 0
        ; initialise the logterm debugging module, if present.
        
        ;; Note: it probably doesn't make sense in minimal angel anyway;
        ;; and certainly would need small changes to work there...
    IF DEBUG = 1 :LAND: LOGTERM_DEBUGGING = 1
        IMPORT  |logterm_Initialise|,WEAK   ; debug initialisation
        BL      logterm_Initialise
    ENDIF

        IMPORT  angel_InitialiseOneOff   ; serialiser initialisation
        IMPORT  angelOS_InitialiseApplication
        IMPORT  angelOS_CPUWrite

        ;; Initialise the serialiser
        BL      angel_InitialiseOneOff          ; init serialiser world

  ENDIF

  IF :DEF: JTAG_ADP_SUPPORTED :LOR: (:DEF: MINIMAL_ANGEL :LAND: MINIMAL_ANGEL<>0)
  ELSE
        
    IF :DEF: ICEMAN_LEVEL_3
        ; set up iceman and library as the application
        IMPORT  Iceman_InitialiseApplication

        LDR     r0, =__entry    ; Application entry point
        BL      Iceman_InitialiseApplication
        
    ELSE
        ; Now we have to set up the application registers so that
        ; the world is ready just for the user to type 'go' from armsd.
                        
        ; angelOS_InitialiseApplication sets up some stuff ...
        LDR     r0, =ADP_HandleUnknown
        MOV     r1, r0
        BL      angelOS_InitialiseApplication

        ; Set up arguments to angelOS_CPUWrite to set PC and CPSR

        ADR     r0, regsetuparea1

        STMFD   sp!, {r0}
        LDR     r0, =ADP_HandleUnknown
        MOV     r1, r0
        LDR     r2, =ADP_CPUmode_Current
        LDR     r3, =ADP_CPUread_PCmode + ADP_CPUread_CPSR
        BL      angelOS_CPUWrite

    ENDIF ; :DEF: ICEMAN_LEVEL_3

  ENDIF   ; NOT :DEF: JTAG_ADP_SUPPORTED :LOR: :DEF: MINIMAL_ANGEL

        ; XXX
        ;
        ; We *should* restore sp here after passing args to angel_OSCPUWrite,
        ; but we don't bother as the first thing __main does is reset sp.
                        
        B       |__main|       ; start higher-level Angel initialisation


regsetuparea1
        DCD     __entry, USRmode

        LTORG

        ; ---------------------------------------------------------------------
        ; The following code fragment is the simple undefined
        ; instruction handler we use when checking for the presence of
        ; a MMU co-processor:
DummyMMUCode
        MOV     r6,#0x00            ; no MMU present if we have aborted
        MOVS    pc,lr               ; return to just after faulting instruction

        ; ---------------------------------------------------------------------

        ADR     a1, fatalmsg
        B       __rt_asm_fatalerror
fatalmsg
        DCB     "Fatal Error\n"
        ALIGN

        ; ---------------------------------------------------------------------

        LTORG

        ; ---------------------------------------------------------------------
        END     ; EOF startrom.s