at91regs.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

/*****************************************************************************
** Confidential
** Copyright (c) 1997 Advanced Risc Machines Limited
** All rights reserved
**
**      Filename : at91regs.h
**      Author   : Mark Snook
**      $Revision$
**   
**  This file is under RCS control
**  RCS $Source$
**  $Id$
**
******************************************************************************
**   Purpose : Header file for AT91 Development Board test programs
**
**
**
******************************************************************************/

#ifndef __AT91REGS_H
#define __AT91REGS_H

/* some debug support for E5 ROM emulator */
#define E5BC_BASE       0x0000FFF0 /* Back channel base address */
#define E5BC_PCDATA	((volatile int *) (E5BC_BASE + 0x00)) /* unused, unused, bc_status, bc_pcdata */

/* base addresses */
#define AT91_MEM        0xFFE00000 /* Memory controller */
#define AT91_SERA	0xFFFD0000 /* Serial port A */
#define AT91_SERB	0xFFFCC000 /* Serial port B */
#define AT91_TIMER      0xFFFE0000 /* Counter/Timer module */
#define AT91_PIO        0xFFFF0000 /* Parallel I/O module */
#define AT91_PMC        0xFFFF4000 /* Power management controller */
#define AT91_WDOG       0xFFFF8000 /* Watchdog timer */
#define AT91_INT        0xFFFFC000 /* Interrupt controller */

/* Serial port registers */
#define SERA_LCR	((volatile int *) (AT91_SERA + 0x00)) /* Port A Line control */
#define SERA_MCR	((volatile int *) (AT91_SERA + 0x04)) /* Port A Mode control */
#define SERA_ICR	((volatile int *) (AT91_SERA + 0x08)) /* Port A Interrupt control */
#define SERA_CSR	((volatile int *) (AT91_SERA + 0x0C)) /* Port A Channel status */
#define SERA_ISR	((volatile int *) (AT91_SERA + 0x10)) /* Port A Interrupt status */
#define SERA_BRG	((volatile int *) (AT91_SERA + 0x14)) /* Port A Baud rate divisor */
#define SERA_RHR	((volatile int *) (AT91_SERA + 0x18)) /* Port A Receive holding */
#define SERA_THR	((volatile int *) (AT91_SERA + 0x1C)) /* Port A Transmit holding */
#define SERA_MAR	((volatile int *) (AT91_SERA + 0x20)) /* Port A Multi-drop address */

#define SERB_LCR	((volatile int *) (AT91_SERB + 0x00)) /* Port B Line control */
#define SERB_MCR	((volatile int *) (AT91_SERB + 0x04)) /* Port B Mode control */
#define SERB_ICR	((volatile int *) (AT91_SERB + 0x08)) /* Port B Interrupt control */
#define SERB_CSR	((volatile int *) (AT91_SERB + 0x0C)) /* Port B Channel status */
#define SERB_ISR	((volatile int *) (AT91_SERB + 0x10)) /* Port B Interrupt status */
#define SERB_BRG	((volatile int *) (AT91_SERB + 0x14)) /* Port B Baud rate divisor */
#define SERB_RHR	((volatile int *) (AT91_SERB + 0x18)) /* Port B Receive holding */
#define SERB_THR	((volatile int *) (AT91_SERB + 0x1C)) /* Port B Transmit holding */
#define SERB_MAR	((volatile int *) (AT91_SERB + 0x20)) /* Port B Multi-drop address */

/* LCR register bits */
#define ENABLE          0x0001
#define FREEZE          0x0002
#define RESETRX         0x0004
#define RESETTX         0x0008
#define ENABLERX        0x0010
#define DISABLERX       0x0020
#define ENABLETX        0x0040
#define DISABELTX       0x0080
#define RESETSTAT       0x0100
#define STARTBRK        0x0200
#define STOPBRK         0x0400
#define RTSON           0x0800 /* not implemented in AT91 */
#define RTSOFF          0x1000 /* not implemented in AT91 */
#define DTRON           0x2000 /* not implemented in AT91 */
#define DTROFF          0x4000 /* not implemented in AT91 */
#define READPARTDATA    0x8000

/* MCR register bits */
#define INTCLK          0x0000
#define INTCLKDIV8      0x0010
#define EXTCLK          0x0020

#define CHAR5BIT        0x0000
#define CHAR6BIT        0x0040
#define CHAR7BIT        0x0080
#define CHAR8BIT        0x00C0

#define ASYNC           0x0000
#define SYNC            0x0100

#define EVEN            0x0000
#define ODD             0x0200

#define PARITYENABLED   0x0000
#define FORCEPARITY     0x0400
#define NOPARITY        0x0800

#define STOP1BIT        0x0000
#define STOP15BIT       0x1000
#define STOP2BIT        0x2000

#define NORMAL          0x0000
#define AUTOECHO        0x4000
#define LOCALLOOPBACK   0x8000
#define REMOTELOOPBACK  0xC000

#define BYTEMODE        0x00000
#define HALFMODE        0x10000
#define WORDMODE        0x20000

#define BAUDRATEOUT     0x40000

/* ICR register bits */
#define ENABLERXREADY   0x0001
#define DISABLERXREADY  0x0002
#define ENABLETXREADY   0x0004
#define DISABLETXREADY  0x0008
#define ENABLEBRC       0x0010
#define DISABLEBRC      0x0020
#define ENABLECTSC      0x0040
#define DISABLECTSC     0x0080
#define ENABLEMCS       0x0100
#define DISABLEMCS      0x0200
#define ENABLEOVERRUN   0x0400
#define DISABLEOVERRUN  0x0800
#define ENABLEFRAME     0x1000
#define DISABLEFRAME    0x2000
#define ENABLEPARITY    0x4000
#define DISABLEPARITY   0x8000
#define RESETBRC        0x10000
#define RESETCTSC       0x20000
#define RESETMCS        0x40000

/* ISR register bits */

#define RXRDY           0x0008
#define TXRDY           0x0010

#define OVERRUNERROR    0x0040
#define FRAMEERROR      0x0080
#define PARITYERROR     0x0100

/* Parallel I/O registers */
#define IO_PORT	        ((volatile int *) (AT91_PIO + 0x00)) /* PIO port data */
#define IO_SET_DATA	((volatile int *) (AT91_PIO + 0x00)) /* PIO set data */
#define IO_CLEAR_DATA	((volatile int *) (AT91_PIO + 0x04)) /* PIO clear data */
#define IO_DATA	        ((volatile int *) (AT91_PIO + 0x04)) /* PIO reg data */
#define IO_FILTER       ((volatile int *) (AT91_PIO + 0x10)) /* PIO filter */
#define IO_DIR          ((volatile int *) (AT91_PIO + 0x20)) /* PIO direction */
#define IO_SEL          ((volatile int *) (AT91_PIO + 0x40)) /* PIO selection */

/* Memory controller registers */
#define MEM_CSR0	((volatile int *) (AT91_MEM + 0x00)) /* CS0 base address */
#define MEM_CSR1	((volatile int *) (AT91_MEM + 0x04)) /* CS1 base address */
#define MEM_CSR2	((volatile int *) (AT91_MEM + 0x08)) /* CS2 base address */
#define MEM_CSR3	((volatile int *) (AT91_MEM + 0x0C)) /* CS3 base address */
#define MEM_RCR 	((volatile int *) (AT91_MEM + 0x20)) /* Remap control */

/* Interrupt controller registers */
#define INT_IVR 	((volatile int *) (AT91_INT + 0x24)) /* Interrupt vector */
#define INT_ISR 	((volatile int *) (AT91_INT + 0x20)) /* Interrupt status */
#define INT_ICR 	((volatile int *) (AT91_INT + 0x14)) /* Interrupt clear */
#define INT_SWI 	((volatile int *) (AT91_INT + 0x10)) /* software interrupt */
#define INT_MRD 	((volatile int *) (AT91_INT + 0x0C)) /* Interrupt mask disable*/
#define INT_MRE 	((volatile int *) (AT91_INT + 0x08)) /* Interrupt mask enable*/
#define INT_ALO 	((volatile int *) (AT91_INT + 0x04)) /* Interrupt mask enable*/
#define INT_SOU 	((volatile int *) (AT91_INT + 0x00)) /* Interrupt mask enable*/

#define INT_IRP0	((volatile int *) (AT91_INT + 0x30)) /* Interrupt priority */
#define INT_IRP1	((volatile int *) (AT91_INT + 0x34)) /* Interrupt priority */
#define INT_IRP2	((volatile int *) (AT91_INT + 0x38)) /* Interrupt priority */
#define INT_IRP3	((volatile int *) (AT91_INT + 0x3C)) /* Interrupt priority */
#define INT_IRP4	((volatile int *) (AT91_INT + 0x40)) /* Interrupt priority */
#define INT_IRP5	((volatile int *) (AT91_INT + 0x44)) /* Interrupt priority */
#define INT_IRP6	((volatile int *) (AT91_INT + 0x48)) /* Interrupt priority */
#define INT_IRP7	((volatile int *) (AT91_INT + 0x4C)) /* Interrupt priority */
#define INT_IRP8	((volatile int *) (AT91_INT + 0x50)) /* Interrupt priority */
#define INT_IRP9	((volatile int *) (AT91_INT + 0x54)) /* Interrupt priority */
#define INT_IRP10	((volatile int *) (AT91_INT + 0x58)) /* Interrupt priority */
#define INT_IRP11	((volatile int *) (AT91_INT + 0x5C)) /* Interrupt priority */
#define INT_IRP16	((volatile int *) (AT91_INT + 0x70)) /* Interrupt priority */
#define INT_IRP17	((volatile int *) (AT91_INT + 0x74)) /* Interrupt priority */
#define INT_IRP18	((volatile int *) (AT91_INT + 0x78)) /* Interrupt priority */

/* Interrupt controller bit positions */
#define FIQBIT          0x00001
#define SOFTBIT         0x00002
#define UART0READYBIT   0x00004
#define UART1READYBIT   0x00008
#define TOUT0BIT        0x00010
#define TOUT1BIT        0x00020
#define TOUT2BIT        0x00040
#define UART0ERRORBIT   0x00080
#define UART1ERRORBIT   0x00100
#define WATCHDOGBIT     0x00200
#define DMA0BIT         0x00400
#define DMA1BIT         0x00800
#define IRQ0BIT         0x10000
#define IRQ1BIT         0x20000
#define IRQ2BIT         0x40000

/* Power management control registers */
#define PMC_PCR 	((volatile int *) (AT91_PMC + 0x00)) /* Power control */

/* Watchdog timer registers */
#define WD_CONT1 	((volatile int *) (AT91_WDOG + 0x00)) /* Watchdog control */
#define WD_CONT2 	((volatile int *) (AT91_WDOG + 0x04)) /* Clock and counter */
#define WD_TIMEOUT 	((volatile int *) (AT91_WDOG + 0x08)) /* Reset timeout */
#define WD_STATUS	((volatile int *) (AT91_WDOG + 0x0C)) /* Status */


#endif

/*****************************************************************************
 * $Log$
 *
 *
 *****************************************************************************/