target.s

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

        SUBT    PIE board description and Angel support         > pie.s
        ; ---------------------------------------------------------------------
        ; This file defines the PIE manifests and macros required
        ; to support the Angel world. It is not a complete description
        ; of the board, only the information necessary for Angel. It
        ; is envisaged that individual device drivers or application
        ; code will hold the necessary definitions for the other board
        ; features.
        ;
        ; NOTE: To help keep the main Angel source as generic as
        ; possible, use is made of macros. However, it is likely
        ; that the use of macros will hide some very obvious and
        ; simple optimisations. If optimised Angel source is required,
        ; then a fixed target version should be created by the porting
        ; developer. The aim of Angel is to be as simple and quick to
        ; port as possible.
        ;
        ; $Revision: 1.9 $
        ;   $Author: hmeeking $
        ;     $Date: 1996/08/20 08:54:35 $
        ;
        ; Copyright Advanced RISC Machines Limited, 1995.
        ; All Rights Reserved
        ;
        ; ---------------------------------------------------------------------

        ASSERT  (listopts_s)
old_opt SETA    {OPT}
        OPT     (opt_off)   ; disable listing of include files

        ; ---------------------------------------------------------------------

        [       (:LNOT: :DEF: pie_s)

                GBLL    pie_s
pie_s       SETL    {TRUE}

        ; ---------------------------------------------------------------------
        ; The "ROMonly" build variable controls whether the system
        ; being built supports a system where only ROM is mapped at
        ; zero, and RAM cannot be mapped there. i.e. where the ARM
        ; vectors are hard-wired in ROM. We create this variable
        ; un-conditionally, to ensure that if an attempt is made to
        ; define it elsewhere then a build error will occur.

                GBLL    ROMonly         ; depends on target
ROMonly         SETL    {FALSE}         ; {TRUE} if no RAM at zero

        ; ---------------------------------------------------------------------
        ; This build variable is for the AT91 board specifically where
    ; the ROM is relocated - as opposed to the PID and PIE cards which
    ; alias the ROM with its true location remaining in memory

                GBLL    REL_ROM_SET     ; depends on target
REL_ROM_SET     SETL    {FALSE}          ; {TRUE} if ROM has no fixed base
                    ; for re-map

        ; ---------------------------------------------------------------------
        ; MMU initialisation manifests.
        ; For the default boot ROM operation we want the cache and
        ; write-buffer to be disabled, so that any external state
        ; monitoring gets a clearer picture of what is happening
        ; within the processor. When a commercial ROM system is being
        ; constructed, i.e. when the final application is being
        ; ROMmed, we should ensure that the cache and writebuffer are
        ; enabled. This can be achieved within the ROM startup code
        ; (INITMMU macro), or later by the actual application.

EnableMMU32             EQU     (Config32 :OR: MMUOn)
EnableMMUCW32           EQU     (Config32 :OR: MMUOn :OR: CacheOn :OR: WriteBufferOn)

        ; ---------------------------------------------------------------------
        ; -- Support macros ---------------------------------------------------
        ; ---------------------------------------------------------------------

        ;; UNMAPROM
        ;; --------
        ;; Provide code to deal with mapping the reset ROM away from zero
        ;; (if required).

        MACRO
$label  UNMAPROM        $w1,$w2

        ; The AT91 is re-mapped by writing 0x1 to the Remap Control
    ; Register (RCR) the remap location is passed in $w1
        MOV     $w2, #1
        STR     $w2, [$w1, #0]
        MEND

        ; STARTUPCODE
        ; -----------
        ; Provide code to deal with ensuring that the
        ; target I/O world is suitably clean before attempting to
        ; initialise the rest of Angel.
        ;
        MACRO
$label  STARTUPCODE     $w1, $w2, $pos, $ramsize

        ;; leave $pos alone - already set - unless we have good reason
        ;; to change it.  Here we don't.

        MOV     $ramsize,#0x00000000    ; RAM size not yet known

    ;; Now we need to set up the memory system for the AT91

    ;; First load in the base address of the memory controller
    ;;LDR   $w1, =AT91_MEM


    ;; Now set up 4 different external memory configurations
    ;;LDR     $w2, =BOOTROMREG
    ;;STR     $w2, [$w1, #0]
    ;;LDR     $w2, =FLASHREG
    ;;STR     $w2, [$w1, #4]
    ;;LDR     $w2, =CSR2DEF
    ;;STR     $w2, [$w1, #8]
    ;;LDR     $w2, =CSR3DEF
    ;;STR     $w2, [$w1, #12]

        MEND

   IF :DEF: AT91_AIC_IRQ
     IF AT91_AIC_IRQ <>0
        ; ---------------------------------------------------------------------
        ; INITAIC
        ; -------
        ; Setup the Advanced Interrupt Controller for the AT91
        ; This routine only sets up the interrupts it doesn't
        ; enable them as we are only interested in the USART
        ; operation here. If more interrupts need to be set up
        ; they could be done here.
        ; The interrupt controller is only set up once, after
        ; this the functions in serial.c clear and re-enable.
        ;
        ; All interrupt sources are given the default handler
        ; to catch any stray interrupts - we don't enable any
        ; other interrupts tho'
        ;
    MACRO
$label  INITAIC         $tmp,$tmp2,$tmp3,$tmp4
    ROUT
$label
    IMPORT DefaultExceptionTable

    LDR $tmp, PtAICBase

    ;; Initialize the Spurious Vector
    ADR     $tmp2, Spurious
    STR     $tmp2, [$tmp, #AIC_SPU]

    ;; First disable the interrupts
    LDR $tmp2,=INT_ALL_SRC
    STR $tmp2, [$tmp, #AIC_IDCR]

    ;; now clear all sources
    LDR $tmp2,=0xFFFFF
    STR $tmp2, [$tmp, #AIC_ICCR]

    ;; Load in the default handler address + 0x18 for IRQ
    LDR $tmp3,=DefaultExceptionTable
    ADD $tmp3, $tmp3, #0x18
    ADD $tmp2, $tmp, #AIC_SVR

    ;; Load a counter for the 32 registers to set default
    LDR $tmp4, =31
10
    STR $tmp3, [$tmp2],#4
    SUBS    $tmp4, $tmp4, #1
    BGT %B10

    ;; Perform 8 End Of Interrupt Command to make sure no interrupt is stacked
    MOV $tmp4, #8
20
    STR $tmp, [$tmp, #AIC_EOICR]
    SUBS    $tmp4, $tmp4, #1
    BGT %B20
    B   EndInitAic

PtAICBase
    DCD         AIC_BASE
Spurious
    sub         r14, r14, #4
    stmfd       sp!, {r14}
    ldr         r14, PtAICBase
    str         r14, [r14, #AIC_EOICR]
    ldmia       sp!, {pc}^

EndInitAic
    MEND


    ENDIF   ; :DEF: AT91_AIC_IRQ
   ENDIF    ; AT91_AIC_IRQ

    ; ---------------------------------------------------------------------
        ; INITMMU
        ; -------
        ; Setup the memory map world for the target. On certain system
        ; where the target does not have a MMU, then this macro can be
        ; a NOP.
        ;
        MACRO
$label  INITMMU         $tmp,$tmp2,$tmp3,$tmp4,$tmp5,$tmp6
        ROUT
$label
        IF :DEF: USE_ARM600_MMU
          ; Setup the ARM600 style MMU with a simple flat page table:
          LDR     $tmp,=angel_MMUtype
          LDR     $tmp,[$tmp]
          CMP     $tmp,#0
          BEQ     %F10
          MCR     MMUCP,0,$tmp,MMUFlushTLBReg,c0  ; Flush the TLB
          MCR     MMUCP,0,$tmp,MMUFlushIDCReg,c0  ; Flush the cache
          LDR     $tmp,=0xFFFFFFFF
          MCR     MMUCP,0,$tmp,MMUDomainAccessReg,c0 ; set domains
          ; The level 1 page table can be found on the next 16K boundary
          ; after the end of the ROM code:
          IMPORT  |Image$$RO$$Limit| ; only valid when building ROM images
          LDR     $tmp,=|Image$$RO$$Limit|        ;
          BIC     $tmp,$tmp,#0x3F00
          BIC     $tmp,$tmp,#0x00FF       ; mask off at 16K boundary
          ADD     $tmp,$tmp,#0x4000       ; bump up to next 16K border
          ; Reference the page table, and initialise the MMU:
          MCR     MMUCP,0,$tmp,MMUPageTableBaseReg,c0 ; Level 1 page table
          ;
          ; See the comments above relating to enabling the cache and
          ; write-buffer. By default this code does not enable either at
          ; the moment.
          MOV     $tmp,#EnableMMU32              ; Default MMU configuration
          MCR     MMUCP,0,$tmp,MMUControlReg,c0  ; Ensure MMU enabled
10

        ELSE
          ; No MMU in the system - do nothing
        ENDIF

        MEND

        ; ---------------------------------------------------------------------
        ; INITTIMER
        ; ---------
        ; This macro is provided purely as a holder for any code that
        ; may be required to initialise a hardware timer as part of
        ; the reset sequence. Angel does *NOT* make use of any timer
        ; resources, so by default this macro should not be required
        ; to do anything. However, under exceptional circumstances
        ; special code may be required to ensure that Angel starts
        ; cleanly and that later application specific code can have
        ; full control of the timer.
        ;
        MACRO
$label  INITTIMER       $w1,$w2
$label  ; No special timer initialisation required for the
        ; PIE. However, certain targets may need to perform I/O
        ; register setup, and start the timer running.
        MEND

        ; ---------------------------------------------------------------------
        ; GETSOURCE
        ; ---------
        ; This macro is used to read the current interrupt source
        ; activity status for the Angel device driver interrupts.
        ;
        ; It can return:
        ;
        ;                  -1 - Ghost Interrupt (no interrupt source active)
        ; DE_NUM_INT_HANDLERS - Interrupt source not recognised
        ;            IH_<xxx> - IntHandlerID (from devconf.h) of Int. source
        ;

        MACRO
$label  GETSOURCE       $w1,$w2
$label  MOV     $w1,#DE_NUM_INT_HANDLERS ; Initally unrecognised interrupt

        ; Now test for specific interrupts. Interrupts tested for
        ; later are given higher priority.


        IF (PARALLEL_SUPPORTED > 0)
          MOV   $w2,#PIObase            ; Reference the PIO
          LDR   $w2,[$w2,#PIO_RSR]      ; Load PIO Rx status
          TST   $w2,#RxDataMask         ; Check for Rx Data
          MOVNE $w1,#IH_PARALLEL        ; Set index accordingly
          BNE   $label.1                ; continue immediately
        ENDIF

        LDR     $w2,=INT_IPR   ; Reference the I/O hardware
        LDR     $w2,[$w2]      ; Load the current Int status
 IF :DEF: PROFILE_SUPPORTED
   IF PROFILE_SUPPORTED <> 0
        TST     $w2,#IMRTimer
        MOVNE   $w1,#IH_TIMER
        BNE     $label.1
   ENDIF
 ENDIF
        TST     $w2,#UART0READYBIT  ; Check for serial source
        MOVNE   $w1,#IH_SERIAL          ; Set index accordingly if active
$label.1
        MEND

        ; ---------------------------------------------------------------------

        ; CACHE_IBR
        ; ---------
        ; This macro implements an instruction barrier for a range of addresses
        ; (i.e. it makes instruction and data memory coherent for this range)
        ; w1 contains the start of the range , w2 the next address after the end
        ; Note that w1 will be corrupted

        ; This will do nothing except for StrongARM systems, where it should
        ; be implemented.
        ;
        MACRO
$label  CACHE_IBR       $w1,$w2
        MEND

        ]       ; pie_s

        OPT     (old_opt)   ; restore previous listing options

        ; ---------------------------------------------------------------------
        END     ; EOF pie.s