📄 lib_at91.lst
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\ at91_clock_set_mode:
\ 00000000 00402DE9 STMDB SP!,{LR} ;; Push
310 //* Depending on the required mode
311 switch (mode)
\ 00000004 010050E3 CMP R0,#+0x1
\ 00000008 0400000A BEQ ??at91_clock_set_mode_0
\ 0000000C 020050E3 CMP R0,#+0x2
\ 00000010 0500000A BEQ ??at91_clock_set_mode_1
\ 00000014 030050E3 CMP R0,#+0x3
\ 00000018 0600000A BEQ ??at91_clock_set_mode_2
312 {
313 //* Idle mode required
314 case PS_MODE_IDLE:
315 //* Write the System Clock Disable Register
316 PS_BASE->PS_CR = PS_ARM7DIS ;
317 break ;
318
319 //* Active all peripheral clocks
320 case PS_ALL_PERIPH_ACTIVE:
321 //* Enable all the peripheral clocks
322 PS_BASE->PS_PCER = 0xFFFFFFFF ;
323 break ;
324
325 //* Desactive all peripheral clocks
326 case PS_ALL_PERIPH_INACTIVE:
327 //* Disable all the peripheral clocks
328 PS_BASE->PS_PCDR = 0xFFFFFFFF ;
329 break ;
330
331 //* EndSwitch
332 }
333 }
\ 0000001C 0080BDE8 LDMIA SP!,{PC} ;; return
\ ??at91_clock_set_mode_0:
\ 00000020 0100A0E3 MOV R0,#+0x1
\ 00000024 FF10E0E3 MVN R1,#+0xFF
\ 00000028 040000EA B ??at91_clock_set_mode_3
\ ??at91_clock_set_mode_1:
\ 0000002C 0000E0E3 MVN R0,#+0x0
\ 00000030 FB10E0E3 MVN R1,#+0xFB
\ 00000034 010000EA B ??at91_clock_set_mode_3
\ ??at91_clock_set_mode_2:
\ 00000038 0000E0E3 MVN R0,#+0x0
\ 0000003C F710E0E3 MVN R1,#+0xF7
\ ??at91_clock_set_mode_3:
\ 00000040 BF1C41E2 SUB R1,R1,#+0xBF00
\ 00000044 000081E5 STR R0,[R1, #+0]
\ 00000048 0080BDE8 LDMIA SP!,{PC} ;; return
334 //* End
335
336 //*----------------------------------------------------------------------------
337 //* Function Name : at91_clock_open
338 //* Object : Enable the peripheral clock
339 //* Input Parameters : <periph_id> = peripheral identifier
340 //* Output Parameters : none
341 //* Functions called : none
342 //*----------------------------------------------------------------------------
\ In segment NEARFUNC_A, align 4, keep-with-next
\ 00000000 CODE32
343 void at91_clock_open ( u_int periph_id )
344 //* Begin
345 {
346 //* Write the Peripheral Clock Enable Register
347 PS_BASE->PS_PCER = (1<<periph_id) ;
\ at91_clock_open:
\ 00000000 0110A0E3 MOV R1,#+0x1
\ 00000004 FF0000E2 AND R0,R0,#+0xFF ;; Zero extend
\ 00000008 1100A0E1 MOV R0,R1, LSL R0
\ 0000000C FB10E0E3 MVN R1,#+0xFB
\ 00000010 ........ B ??Subroutine1_0
348 //* End
349 }
350
351 //*----------------------------------------------------------------------------
352 //* Function Name : at91_clock_close
353 //* Object : Disable the clock of a Peripheral
354 //* Input Parameters : <periph_id> = peripheral identifier
355 //* Output Parameters : none
356 //* Functions called : none
357 //*----------------------------------------------------------------------------
\ In segment NEARFUNC_A, align 4, keep-with-next
\ 00000000 CODE32
358 void at91_clock_close ( u_int periph_id )
\ at91_clock_close:
\ 00000000 REQUIRE ??Subroutine1_0
359 //* Begin
360 {
361 //* Write the Peripheral Clock Disable Register
362 PS_BASE->PS_PCDR = (1<<periph_id) ;
\ 00000000 0110A0E3 MOV R1,#+0x1
\ 00000004 FF0000E2 AND R0,R0,#+0xFF ;; Zero extend
\ 00000008 1100A0E1 MOV R0,R1, LSL R0
\ 0000000C F710E0E3 MVN R1,#+0xF7
363 //* End
364 }
\ In segment NEARFUNC_A, align 4, keep-with-next
\ ??Subroutine1_0:
\ 00000000 BF1C41E2 SUB R1,R1,#+0xBF00
\ ??Subroutine1_1:
\ 00000004 000081E5 STR R0,[R1, #+0]
\ 00000008 0EF0A0E1 MOV PC,LR ;; return
365
366 //*----------------------------------------------------------------------------
367 //* Function Name : at91_clock_get_status
368 //* Object : Return the Peripheral clock status
369 //* Input Parameters : <periph_id> = peripheral identifier
370 //* Output Parameters : none
371 //* Functions called : none
372 //*----------------------------------------------------------------------------
\ In segment NEARFUNC_A, align 4, keep-with-next
\ 00000000 CODE32
373 u_int at91_clock_get_status ( u_int periph_id )
374 //* Begin
375 {
376 //* Return the Peripheral Clock Status Register
377 return ( PS_BASE->PS_PCSR & (1<<periph_id) ) ;
\ at91_clock_get_status:
\ 00000000 F310E0E3 MVN R1,#+0xF3
\ 00000004 BF1C41E2 SUB R1,R1,#+0xBF00
\ 00000008 002091E5 LDR R2,[R1, #+0]
\ 0000000C 0110A0E3 MOV R1,#+0x1
\ 00000010 FF0000E2 AND R0,R0,#+0xFF ;; Zero extend
\ 00000014 110002E0 AND R0,R2,R1, LSL R0
\ 00000018 0EF0A0E1 MOV PC,LR ;; return
378 //* End
379 }
380
381 //*----------------------------------------------------------------------------
382 //* Function Name : at91_usart_open
383 //* Object : Initialize an USART.
384 //* Input Parameters : <usart_pt> = the USART to initialize
385 //* : <mode> = the Mode Register to be programmed
386 //* : <speed> = the BRDR to be programmed
387 //* : <timeguard> = the US_TTGR to be programmed
388 //* Output Parameters : None
389 //* Functions called : at91_clock_open, at91_pio_close
390 //*----------------------------------------------------------------------------
\ In segment NEARFUNC_A, align 4, keep-with-next
\ 00000000 CODE32
391 void at91_usart_open ( const UsartDesc *usart_pt ,
392 u_int mode ,
393 u_int speed ,
394 u_int timeguard )
395 //* Begin
396 {
\ at91_usart_open:
\ 00000000 F0412DE9 STMDB SP!,{R4-R8,LR} ;; Push
\ 00000004 0040A0E1 MOV R4,R0
\ 00000008 0150A0E1 MOV R5,R1
\ 0000000C 0260A0E1 MOV R6,R2
\ 00000010 0370A0E1 MOV R7,R3
397 //* Enable the clock
398 at91_clock_open ( usart_pt->periph_id ) ;
\ 00000014 0480A0E1 MOV R8,R4
\ 00000018 0B00D8E5 LDRB R0,[R8, #+11]
\ 0000001C ........ BL at91_clock_open
399
400 //* If External clock used
401 if (( mode & SCK_USED ) != 0 )
\ 00000020 2000A0E3 MOV R0,#+0x20
\ 00000024 010780E2 ADD R0,R0,#+0x40000
\ 00000028 000015E1 TST R5,R0
\ 0000002C 0100A0E3 MOV R0,#+0x1
\ 00000030 0910D8E5 LDRB R1,[R8, #+9]
\ 00000034 0020A0E1 MOV R2,R0
\ 00000038 0830D8E5 LDRB R3,[R8, #+8]
\ 0000003C 1223A0E1 MOV R2,R2, LSL R3
\ 00000040 0400000A BEQ ??at91_usart_open_0
402 {
403 //* Define RXD, TXD and SCK as peripheral
404 at91_pio_close ( usart_pt->pio_ctrl,
405 (1 << usart_pt->pin_txd) |
406 (1 << usart_pt->pin_rxd) |
407 (1 << usart_pt->pin_sck) ) ;
\ 00000044 100182E1 ORR R0,R2,R0, LSL R1
\ 00000048 0110A0E3 MOV R1,#+0x1
\ 0000004C 0A20D8E5 LDRB R2,[R8, #+10]
\ 00000050 111280E1 ORR R1,R0,R1, LSL R2
\ 00000054 000000EA B ??at91_usart_open_1
408 }
409 //* Else
410 else
411 {
412 //* Define RXD and TXD as peripheral
413 at91_pio_close ( usart_pt->pio_ctrl,
414 (1 << usart_pt->pin_txd) |
415 (1 << usart_pt->pin_rxd) ) ;
\ ??at91_usart_open_0:
\ 00000058 101182E1 ORR R1,R2,R0, LSL R1
\ ??at91_usart_open_1:
\ 0000005C 040098E5 LDR R0,[R8, #+4]
\ 00000060 ........ BL at91_pio_close
416 //* EndIf
417 }
418
419 //* Reset receiver and transmitter
420 usart_pt->usart_base->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS ;
\ 00000064 AC00A0E3 MOV R0,#+0xAC
\ 00000068 001098E5 LDR R1,[R8, #+0]
\ 0000006C 000081E5 STR R0,[R1, #+0]
421
422 //* Clear Transmit and Receive Counters
423 usart_pt->usart_base->US_RCR = 0 ;
\ 00000070 0000A0E3 MOV R0,#+0x0
\ 00000074 001098E5 LDR R1,[R8, #+0]
\ 00000078 340081E5 STR R0,[R1, #+52]
424 usart_pt->usart_base->US_TCR = 0 ;
\ 0000007C 001098E5 LDR R1,[R8, #+0]
\ 00000080 3C0081E5 STR R0,[R1, #+60]
425
426 //* Define the baud rate divisor register
427 usart_pt->usart_base->US_BRGR = speed ;
\ 00000084 000098E5 LDR R0,[R8, #+0]
\ 00000088 206080E5 STR R6,[R0, #+32]
428
429 //* Define the USART mode
430 usart_pt->usart_base->US_MR = mode ;
\ 0000008C 000098E5 LDR R0,[R8, #+0]
\ 00000090 045080E5 STR R5,[R0, #+4]
431
432 //* Write the Timeguard Register
433 usart_pt->usart_base->US_TTGR = timeguard ;
\ 00000094 000098E5 LDR R0,[R8, #+0]
\ 00000098 287080E5 STR R7,[R0, #+40]
434
435 //* Enable receiver and transmitter
436 usart_pt->usart_base->US_CR = US_RXEN | US_TXEN ;
\ 0000009C 5000A0E3 MOV R0,#+0x50
\ 000000A0 001098E5 LDR R1,[R8, #+0]
\ 000000A4 000081E5 STR R0,[R1, #+0]
437
438 //* End
439 }
\ 000000A8 F081BDE8 LDMIA SP!,{R4-R8,PC} ;; return
440
441 //*----------------------------------------------------------------------------
442 //* Function Name : at91_usart_close
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