at91irq_asm_handler.arm

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

;***************************************************************************
;* File Name 	: At91irq_asm_handler1.arm
;*
;* Description	: Define the ARM7 vector area.  This should be located or
;* 		  copied to 0.
;*
;* George Zhang : 08/25/2000
;*		  10/12/2000
;***************************************************************************

/**************************************************************************/
/**************************************************************************/
/**                                                                       */ 
/** ThreadX Component                                                     */ 
/**                                                                       */
/**   Initialize (INI)                                                    */
/**                                                                       */
/**************************************************************************/
/**************************************************************************/
	EXPORT	__tx_timer_handler
	EXPORT	__at91_usart0_handler
	EXPORT	__at91_irq0_handler

	INCLUDE     "../../periph/arm7tdmi/arm.inc"
	INCLUDE     "../../periph/aic/aic.inc"
	INCLUDE     "../../periph/timer_counter/tc.inc"

;	 INCLUDE     "../../parts/m40400/m40400.inc"
/**************************************************************************/
    TC0_BASE        EQU     0xFFFE0000      ; Timer0 address
    ; TC0_BASE is included in "../../parts/m40400/m40400.inc"
    ; but difficult to build the path - George
/**************************************************************************/

    TC0_SOURCE_VECTOR = 0xFFFFF090      ; Address of Timer0 Vector register
    TC0_SOURCE_MODE =	0xFFFFF010      ; Address of Timer0 Source Mode register
    TC0_IRQEN_BIT  =    0x10            ; Timer 0 IRQ enable bit map

    TX_TC0_IRQ_MODE =  	0x21            ; Timre 0 IRQ mode for ThreadX
    TX_TC0_MODE  =     	0xC001          ; Timer 0 Channel Mode for ThreadX, MCK/8
    TX_TICK_RATE =      0x8FFF          ; System tick rate for ThreadX
    					; TICK RATE = TX_TICK_RATE*2/MCK (s)


    .text
    .align  4
/**************************************************************************/ 
/*                                                                        */ 
/*  FUNCTION	: _tx_initialize_low_level                                */ 
/*                                                                        */ 
/*  DESCRIPTION	: This function is responsible for any low-level AT91     */
/*		  processor initialization, including setting up interrupt*/
/*		  vectors, saving the system stack pointer, finding the   */
/*		  first available memory address, and setting up 	  */
/*		  parameters for the system's timer thread.               */ 
/*                                                                        */ 
/*  INPUT	: None                                                    */ 
/*                                                                        */ 
/*  OUTPUT	: None                                                    */ 
/*                                                                        */ 
/*  CALLS	: None                                                    */ 
/*                                                                        */ 
/*  CALLED BY	: _tx_initialize_kernel_enter (ThreadX entry C function)  */ 
/*                                                                        */ 
/**************************************************************************/ 
    .globl  _tx_initialize_low_level
_tx_initialize_low_level:

    /* **** NOTE **** We must be in SVC MODE at this point.  Some monitors */
    /* enter this routine in USER mode and require a software interrupt to */
    /* change into SVC mode.  						   */

    /* Save the system stack pointer.  */
    /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp);  */
    LDR     a2, SYS_STACK_PTR               ; Pickup address of system stack ptr
    STR     sp, [a2]                        ; Save system stack 

    /* Pickup the first available memory address.  */
    LDR     a1, FREE_MEMORY                 ; Pickup free memory address

    /* Setup initial stack pointers for IRQ and FIQ modes.  */
    MOV     a2, a1                          ; Get first available memory
    LDR     a3, FIQ_STACK_SIZE              ; Pickup stack size
    MOV     a4, ARM_MODE_FIQ                ; Build FIQ mode CPSR
    MSR     CPSR_cxsf, a4                   ; Enter FIQ mode
    ADD     a2, a2, a3                      ; Calculate start of FIQ stack
    BIC     a2, a2, 3                       ; Insure long word alignment
    SUB     a2, a2, 4                       ; Backup one word
    MOV     sp, a2                          ; Setup FIQ stack pointer
    MOV     sl, 0                           ; Clear sl
    MOV     fp, 0                           ; Clear fp
    LDR     a3, IRQ_STACK_SIZE              ; Pickup IRQ (system stack size)
    MOV     a4, ARM_MODE_IRQ                ; Build IRQ mode CPSR
    MSR     CPSR_cxsf, a4                   ; Enter IRQ mode
    ADD     a2, a2, a3                      ; Calculate start of IRQ stack
    BIC     a2, a2, 3                       ; Insure long word alignment
    SUB     a2, a2, 4                       ; Backup one word
    MOV     sp, a2                          ; Setup IRQ stack pointer
    MOV     a4, ARM_MODE_SVC                ; Build SVC mode CPSR
    MSR     CPSR_cxsf, a4                   ; Enter SVC mode
    ADD     a1, a2, 4                       ; Addjust the new fee memory

    /* Allocate space for the timer thread's stack.  */

    LDR     a2, TIMER_STACK                 ; Pickup timer stack ptr address
    LDR     a4, TIMER_STACK_SIZE            ; Pickup timer stack size address
    LDR     a3, TIM_STACK_SIZE              ; Pickup actual stack size
    STR     a1, [a2]                        ; Store timer stack base
    STR     a3, [a4]                        ; Store timer stack size
    ADD     a1, a1, a3                      ; New free memory address
    LDR     a2, TIMER_PRIORITY              ; Pickup timer priority address
    MOV     a3, 0                           ; Build timer thread priority
    STR     a3, [a2]                        ; Store timer thread priority

    /* Save the first available memory address.  */
    /* _tx_initialize_unused_memory =  (VOID_PTR) System Stack + Timer Stack;  */
    LDR     a3, UNUSED_MEMORY               ; Pickup unused memory ptr address
    STR     a1, [a3]                        ; Save first free memory address

    /* Setup AT91 Timer0 for periodic interrupts.  */
    LDR     a3,=TC0_SOURCE_VECTOR           ; Build address of timer's vector (vector 4)
    LDR     a2, TIMER_HANDLER               ; Build address of actual timer vector 
    STR     a2, [a3]                        ; Setup timer vector
    LDR     a3,=TC0_SOURCE_MODE             ; Build address of timer vector's mode
    LDR     a2,=TX_TC0_IRQ_MODE             ; Build mode value
    STR     a2, [a3]                        ; Setup timer0 vector mode
    LDR     a3,=AIC_BASE                    ; Build address of interrupt enable register
    LDR     a2,=TC0_IRQEN_BIT               ; Build interrupt enable value
    STR     a2, [a3, #AIC_IECR]             ; Enable timer0 interrupts
    LDR     a3,=TC0_BASE                    ; Build address of timer channel mode register
    LDR     a2,=TX_TC0_MODE                 ; Build mode value selection
    STR     a2, [a3, #TC_CMR]               ; Setup timer mode
    LDR     a3,=TC0_BASE                    ; Build address of timer interrupt enable register
    LDR     a2,=TC0_IRQEN_BIT               ; Build timer0 interrupt enable value
    STR     a2, [a3, #TC_IER]               ; Enable timer0 interrupts
    LDR     a3,=TC0_BASE                    ; Build address of timer status register
    LDR     a2, [a3, #TC_SR]                ; Read status register
    LDR     a3,=TC0_BASE                    ; Build address of timer interrupt disable register
    MOV     a2, 0                           ; Build clear value
    STR     a2, [a3, #TC_IDR]               ; Make sure timer interrupt disable is clear
    LDR     a3,=TC0_BASE                    ; Build address of timer interrupt mask register
    LDR     a2,=TC0_IRQEN_BIT               ; Build timer0 interrupt enable value
    STR     a2, [a3, #TC_IMR]               ; Enable timer0 interrupts
    LDR     a3,=TC0_BASE                    ; Build address of timer count value register
    MOV     a2, 0                           ; Build clear value
    STR     a2, [a3, #TC_CV]                ; Clear timer count register
    LDR     a3,=TC0_BASE                    ; Build address of register C
    LDR     a2,=TX_TICK_RATE                ; Set tick rate value
    STR     a2, [a3, #TC_RC]                ; Setup timer register C
    LDR     a3,=TC0_BASE                    ; Build address of timer channel control register
    LDR     a2,=TC_CLKEN                    ; Build timer enable value
    STR     a2, [a3, #TC_CCR]               ; Enable the timer
    LDR     a2,=TC_SWTRG                    ; Build timer sync value
    STR     a2, [a3]                        ; Start the timer running!

    /* Done, return to caller.  */
    RET                                     ; Return to caller