📄 cstartup.paf.arm
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#define TOP_EXCEPTION_STACK RAM_LIMIT
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#define TOP_APPLICATION_STACK EXT_SRAM_LIMIT
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ldr r0, =TOP_EXCEPTION_STACK
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msr CPSR_c, ARM_MODE_FIQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, FIQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, IRQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_ABORT | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, ABT_STACK_SIZE
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msr CPSR_c, ARM_MODE_UNDEF | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, UND_STACK_SIZE
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msr CPSR_c, ARM_MODE_SVC | I_BIT | F_BIT
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mov r13, r0
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msr CPSR_c, ARM_MODE_USER
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ldr r13, =TOP_APPLICATION_STACK
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.weak __ghsbegin_bss
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.weak __ghsend_bss
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ldr r1, =__ghsend_bss
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ldr r3, =__ghsbegin_bss
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mov r2, 0
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LoopZI
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cmp r3, r1
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strcc r2, [r3], 4
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bcc LoopZI
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.weak __ghsbegin_sbss
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.weak __ghsend_sbss
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ldr r1, =__ghsend_sbss
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ldr r3, =__ghsbegin_sbss
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mov r2, 0
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LoopZI2
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cmp r3, r1
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strcc r2, [r3], 4
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bcc LoopZI2
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#if defined(SEMIHOSTING)
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#define SEMIHOSTING_STACK_SIZE (8*1024)
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ldr r0, = SEMIHOSTING_STACK_SIZE
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sub r13, r13,r0
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.weak __ghsbegin_robase
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mov fp, 0
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ldr r0, pool_baseptrs
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bl __ghs_ind_crt0
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pool_baseptrs:
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.data.w baseptrs
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baseptrs:
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.data.w __ghsbegin_picbase
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.data.w __ghsbegin_robase
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.data.w __ghsbegin_pidbase
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#else
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IMPORT main
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ldr r0, =main
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mov lr, pc
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bx r0
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#endif
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End
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b End
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.type __main, $function
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.size __main,.-__main
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/*END*/
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__low_level_init
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mov pc,r14
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#endif
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#if defined(AT91_DEBUG_ICE)
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;.section ".reset","ax"
;.reset
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EXPORT __main
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__main
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B InitReset
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undefvec
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B undefvec
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swivec
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B swivec
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pabtvec
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B pabtvec
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dabtvec
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B dabtvec
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rsvdvec
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B rsvdvec
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irqvec
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B irqvec
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fiqvec
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B fiqvec
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VectorTable
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ldr pc, [pc, 0x18]
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ldr pc, [pc, 0x18]
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ldr pc, [pc, 0x18]
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ldr pc, [pc, 0x18]
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ldr pc, [pc, 0x18]
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nop
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ldr pc, [pc,-0xF20]
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ldr pc, [pc,-0xF20]
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.word SoftReset
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.word UndefHandler
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.word SWIHandler
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.word PrefetchAbortHandler
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.word DataAbortHandler
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SoftReset
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b SoftReset
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UndefHandler
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b UndefHandler
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SWIHandler
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b SWIHandler
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PrefetchAbortHandler
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b PrefetchAbortHandler
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DataAbortHandler
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b DataAbortHandler
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InitTableEBI
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.word EBI_CSR_0
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.word EBI_CSR_1
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.word EBI_CSR_2
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.word EBI_CSR_3
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.word EBI_CSR_4
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.word EBI_CSR_5
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.word EBI_CSR_6
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.word EBI_CSR_7
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.word 0x00000001
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.word 0x00000006
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PtEBIBase
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.word EBI_BASE
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InitReset
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ldr r0, PtEBIBase
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ldr r1, [pc,-(8+.-InitTableEBI)]
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str r1, [r0]
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bl __low_level_init
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add r0, pc,AicData-8-.
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ldmia r0, {r1-r4}
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str r4, [r1, 0x134]
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mov r0, 8
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LoopAic0
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str r1, [r1, 0x130]
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subs r0, r0, 1
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bhi LoopAic0
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str r2, [r1, 0x80]
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add r1, r1, 0x80
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mov r0, 31
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LoopAic1
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str r3, [r1, r0, LSL 2]
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subs r0, r0, 1
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bhi LoopAic1
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b EndInitAic
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AicData
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.word AIC_BASE
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IMPORT at91_default_fiq_handler
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IMPORT at91_default_irq_handler
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IMPORT at91_spurious_handler
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PtDefaultHandler
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.word at91_default_fiq_handler
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.word at91_default_irq_handler
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.word at91_spurious_handler
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EndInitAic
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mov r8,RAM_BASE
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sub r9, pc,.-VectorTable+8
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ldmia r9!, {r0-r7}
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#if defined(SEMIHOSTING )
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stmia r8!, {r0-r1}
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add r8, r8,4
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stmia r8!, {r3-r7}
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#else
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stmia r8!, {r0-r7}
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#endif
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ldmia r9!, {r0-r4}
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stmia r8!, {r0-r4}
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sub r10, pc,(8+.-InitTableEBI)
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ldr r12, PtInitRemap
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ldmia r10!, {r0-r9,r11}
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stmia r11!, {r0-r9}
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mov pc, r12
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PtInitRemap
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.word InitRemap
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InitRemap
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#define IRQ_STACK_SIZE (3*8*4)
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#define FIQ_STACK_SIZE (3*4)
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#define ABT_STACK_SIZE (1*4)
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#define UND_STACK_SIZE (1*4)
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#define TOP_EXCEPTION_STACK RAM_LIMIT
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#define TOP_APPLICATION_STACK EXT_SRAM_LIMIT
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ldr r0, =TOP_EXCEPTION_STACK
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msr CPSR_c, ARM_MODE_FIQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, FIQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, IRQ_STACK_SIZE
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msr CPSR_c, ARM_MODE_ABORT | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, ABT_STACK_SIZE
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msr CPSR_c, ARM_MODE_UNDEF | I_BIT | F_BIT
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mov r13, r0
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sub r0, r0, UND_STACK_SIZE
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msr CPSR_c, ARM_MODE_SVC | I_BIT | F_BIT
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mov r13, r0
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msr CPSR_c, ARM_MODE_USER
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ldr r13, =TOP_APPLICATION_STACK
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.weak __ghsbegin_bss
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.weak __ghsend_bss
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ldr r1, =__ghsend_bss
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ldr r3, =__ghsbegin_bss
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mov r2, 0
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LoopZI
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cmp r3, r1
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strcc r2, [r3], 4
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bcc LoopZI
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.weak __ghsbegin_sbss
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