hw.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

#   endif
#endif

/* Parallel I/O registers */
#define PIO_PER         ((volatile int *) (AT91_PIO + 0x00)) /* PIO Enable */
#define PIO_PDR         ((volatile int *) (AT91_PIO + 0x04)) /* PIO Disable */
#define IO_DATA         ((volatile int *) (AT91_PIO + 0x04)) /* PIO reg data */
#define IO_FILTER       ((volatile int *) (AT91_PIO + 0x10)) /* PIO filter */
#define IO_DIR          ((volatile int *) (AT91_PIO + 0x20)) /* PIO direction */
#define IO_SEL          ((volatile int *) (AT91_PIO + 0x40)) /* PIO selection */
#define PIO_SODR        ((volatile int *) (AT91_PIO + 0x30)) /* PIO Enable */
#define PIO_CODR        ((volatile int *) (AT91_PIO + 0x34)) /* PIO Disable */

#ifdef ___EB01
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFF0004)
#define PIO_US0         0xC000
#define PIO_US1         0x60000
#endif

#ifdef ___EB40
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFF0004)
#define PIO_US0         0xC000
#define PIO_US1         0x60000
#endif

#ifdef ___EB40A
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFF0004)
#define PIO_US0         0xC000
#define PIO_US1         0x60000
#endif

#ifdef ___EB42
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFEC004)
#define PIO_US0         0xC0
#define PIO_US1         0x700
#endif

#ifdef ___EB55
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFEC004)
#define PIO_US0         0x18000
#define PIO_US1         0xC0000
#endif

#ifdef ___EB63
#define PIO_PDR_USART   ((volatile unsigned int *) 0xFFFEC004)
#define PIO_US0         0x18000
#define PIO_US1         0xC0000
#endif

#define LED1BIT         0x10
#define LED2BIT         0x02

#define LED1            0x1
#define LED2            0x2

/* Memory controller registers */
#define MEM_CSR0    ((volatile int *) (AT91_MEM + 0x00)) /* CS0 base address */
#define MEM_CSR1    ((volatile int *) (AT91_MEM + 0x04)) /* CS1 base address */
#define MEM_CSR2    ((volatile int *) (AT91_MEM + 0x08)) /* CS2 base address */
#define MEM_CSR3    ((volatile int *) (AT91_MEM + 0x0C)) /* CS3 base address */
#define MEM_RCR     ((volatile int *) (AT91_MEM + 0x20)) /* Remap control */

/* Interrupt controller registers */

#define INT_SMR0        ((volatile int *) (AT91_INT + 0x00)) /* Interrupt vector */
#define INT_SMR1        ((volatile int *) (AT91_INT + 0x04)) /* Interrupt vector */
#define INT_SMR2        ((volatile int *) (AT91_INT + 0x08)) /* Interrupt vector */
#define INT_SMR3        ((volatile int *) (AT91_INT + 0x0C)) /* Interrupt vector */
#define INT_SMR4        ((volatile int *) (AT91_INT + 0x10)) /* Interrupt vector */
#define INT_SMR5        ((volatile int *) (AT91_INT + 0x14)) /* Interrupt vector */
#define INT_SMR6        ((volatile int *) (AT91_INT + 0x18)) /* Interrupt vector */
#define INT_SMR7        ((volatile int *) (AT91_INT + 0x1C)) /* Interrupt vector */
#define INT_SMR8        ((volatile int *) (AT91_INT + 0x20)) /* Interrupt vector */
#define INT_SMR9        ((volatile int *) (AT91_INT + 0x24)) /* Interrupt vector */
#define INT_SMR10       ((volatile int *) (AT91_INT + 0x28)) /* Interrupt vector */
#define INT_SMR11       ((volatile int *) (AT91_INT + 0x2C)) /* Interrupt vector */
#define INT_SMR12       ((volatile int *) (AT91_INT + 0x30)) /* Interrupt vector */
#define INT_SMR13       ((volatile int *) (AT91_INT + 0x34)) /* Interrupt vector */
#define INT_SMR14       ((volatile int *) (AT91_INT + 0x38)) /* Interrupt vector */
#define INT_SMR15       ((volatile int *) (AT91_INT + 0x3C)) /* Interrupt vector */
#define INT_SMR16       ((volatile int *) (AT91_INT + 0x40)) /* Interrupt vector */
#define INT_SMR17       ((volatile int *) (AT91_INT + 0x44)) /* Interrupt vector */
#define INT_SMR18       ((volatile int *) (AT91_INT + 0x48)) /* Interrupt vector */
#define INT_SMR19       ((volatile int *) (AT91_INT + 0x4C)) /* Interrupt vector */
#define INT_SMR20       ((volatile int *) (AT91_INT + 0x50)) /* Interrupt vector */
#define INT_SMR21       ((volatile int *) (AT91_INT + 0x54)) /* Interrupt vector */
#define INT_SMR22       ((volatile int *) (AT91_INT + 0x58)) /* Interrupt vector */
#define INT_SMR23       ((volatile int *) (AT91_INT + 0x5C)) /* Interrupt vector */
#define INT_SMR24       ((volatile int *) (AT91_INT + 0x60)) /* Interrupt vector */
#define INT_SMR25       ((volatile int *) (AT91_INT + 0x64)) /* Interrupt vector */
#define INT_SMR26       ((volatile int *) (AT91_INT + 0x68)) /* Interrupt vector */
#define INT_SMR27       ((volatile int *) (AT91_INT + 0x6C)) /* Interrupt vector */
#define INT_SMR28       ((volatile int *) (AT91_INT + 0x70)) /* Interrupt vector */
#define INT_SMR29       ((volatile int *) (AT91_INT + 0x74)) /* Interrupt vector */
#define INT_SMR30       ((volatile int *) (AT91_INT + 0x78)) /* Interrupt vector */
#define INT_SMR31       ((volatile int *) (AT91_INT + 0x7C)) /* Interrupt vector */

#define INT_SVR0        ((volatile int *) (AT91_INT + 0x80)) /* Interrupt vector */
#define INT_SVR1        ((volatile int *) (AT91_INT + 0x84)) /* Interrupt vector */
#define INT_SVR2        ((volatile int *) (AT91_INT + 0x88)) /* Interrupt vector */
#define INT_SVR3        ((volatile int *) (AT91_INT + 0x8C)) /* Interrupt vector */
#define INT_SVR4        ((volatile int *) (AT91_INT + 0x90)) /* Interrupt vector */
#define INT_SVR5        ((volatile int *) (AT91_INT + 0x94)) /* Interrupt vector */
#define INT_SVR6        ((volatile int *) (AT91_INT + 0x98)) /* Interrupt vector */
#define INT_SVR7        ((volatile int *) (AT91_INT + 0x9C)) /* Interrupt vector */
#define INT_SVR8        ((volatile int *) (AT91_INT + 0xA0)) /* Interrupt vector */
#define INT_SVR9        ((volatile int *) (AT91_INT + 0xA4)) /* Interrupt vector */
#define INT_SVR10       ((volatile int *) (AT91_INT + 0xA8)) /* Interrupt vector */
#define INT_SVR11       ((volatile int *) (AT91_INT + 0xAC)) /* Interrupt vector */
#define INT_SVR12       ((volatile int *) (AT91_INT + 0xB0)) /* Interrupt vector */
#define INT_SVR13       ((volatile int *) (AT91_INT + 0xB4)) /* Interrupt vector */
#define INT_SVR14       ((volatile int *) (AT91_INT + 0xB8)) /* Interrupt vector */
#define INT_SVR15       ((volatile int *) (AT91_INT + 0xBC)) /* Interrupt vector */
#define INT_SVR16       ((volatile int *) (AT91_INT + 0xC0)) /* Interrupt vector */
#define INT_SVR17       ((volatile int *) (AT91_INT + 0xC4)) /* Interrupt vector */
#define INT_SVR18       ((volatile int *) (AT91_INT + 0xC8)) /* Interrupt vector */
#define INT_SVR19       ((volatile int *) (AT91_INT + 0xCC)) /* Interrupt vector */
#define INT_SVR20       ((volatile int *) (AT91_INT + 0xD0)) /* Interrupt vector */
#define INT_SVR21       ((volatile int *) (AT91_INT + 0xD4)) /* Interrupt vector */
#define INT_SVR22       ((volatile int *) (AT91_INT + 0xD8)) /* Interrupt vector */
#define INT_SVR23       ((volatile int *) (AT91_INT + 0xDC)) /* Interrupt vector */
#define INT_SVR24       ((volatile int *) (AT91_INT + 0xE0)) /* Interrupt vector */
#define INT_SVR25       ((volatile int *) (AT91_INT + 0xE4)) /* Interrupt vector */
#define INT_SVR26       ((volatile int *) (AT91_INT + 0xE8)) /* Interrupt vector */
#define INT_SVR27       ((volatile int *) (AT91_INT + 0xEC)) /* Interrupt vector */
#define INT_SVR28       ((volatile int *) (AT91_INT + 0xF0)) /* Interrupt vector */
#define INT_SVR29       ((volatile int *) (AT91_INT + 0xF4)) /* Interrupt vector */
#define INT_SVR30       ((volatile int *) (AT91_INT + 0xF8)) /* Interrupt vector */
#define INT_SVR31       ((volatile int *) (AT91_INT + 0xFC)) /* Interrupt vector */

#define INT_IVR         ((volatile int *) (AT91_INT + 0x100)) /* Interrupt vector */
#define INT_FVR         ((volatile int *) (AT91_INT + 0x100)) /* Interrupt vector */
#define INT_ISR         ((volatile int *) (AT91_INT + 0x108)) /* Interrupt vector */
#define INT_IPR         ((volatile int *) (AT91_INT + 0x10C)) /* Interrupt vector */
#define INT_IMR         ((volatile int *) (AT91_INT + 0x110)) /* Interrupt vector */
#define INT_CISR        ((volatile int *) (AT91_INT + 0x114)) /* Interrupt vector */
#define INT_IECR        ((volatile int *) (AT91_INT + 0x120)) /* Interrupt vector */
#define INT_IDCR        ((volatile int *) (AT91_INT + 0x124)) /* Interrupt vector */
#define INT_ICCR        ((volatile int *) (AT91_INT + 0x128)) /* Interrupt vector */
#define INT_ISCR         ((volatile int *) (AT91_INT + 0x12C)) /* Interrupt vector */
#define INT_EICR        ((volatile int *) (AT91_INT + 0x130)) /* Interrupt vector */


#define INT_IRP0    ((volatile int *) (AT91_INT + 0x30)) /* Interrupt priority */
#define INT_IRP1    ((volatile int *) (AT91_INT + 0x34)) /* Interrupt priority */
#define INT_IRP2    ((volatile int *) (AT91_INT + 0x38)) /* Interrupt priority */
#define INT_IRP3    ((volatile int *) (AT91_INT + 0x3C)) /* Interrupt priority */
#define INT_IRP4    ((volatile int *) (AT91_INT + 0x40)) /* Interrupt priority */
#define INT_IRP5    ((volatile int *) (AT91_INT + 0x44)) /* Interrupt priority */
#define INT_IRP6    ((volatile int *) (AT91_INT + 0x48)) /* Interrupt priority */
#define INT_IRP7    ((volatile int *) (AT91_INT + 0x4C)) /* Interrupt priority */
#define INT_IRP8    ((volatile int *) (AT91_INT + 0x50)) /* Interrupt priority */
#define INT_IRP9    ((volatile int *) (AT91_INT + 0x54)) /* Interrupt priority */
#define INT_IRP10   ((volatile int *) (AT91_INT + 0x58)) /* Interrupt priority */
#define INT_IRP11   ((volatile int *) (AT91_INT + 0x5C)) /* Interrupt priority */
#define INT_IRP16   ((volatile int *) (AT91_INT + 0x70)) /* Interrupt priority */
#define INT_IRP17   ((volatile int *) (AT91_INT + 0x74)) /* Interrupt priority */
#define INT_IRP18   ((volatile int *) (AT91_INT + 0x78)) /* Interrupt priority */

/* Interrupt controller bit positions */
#define FIQBIT          0x00001
#define SOFTBIT         0x00002
#define UART0READYBIT   0x00004
#define UART1READYBIT   0x00008
#define TOUT0BIT        0x00010
#define TOUT1BIT        0x00020
#define TOUT2BIT        0x00040
#define UART0ERRORBIT   0x00080
#define UART1ERRORBIT   0x00100
#define WATCHDOGBIT     0x00200
#define DMA0BIT         0x00400
#define DMA1BIT         0x00800
#define IRQ0BIT         0x10000
#define IRQ1BIT         0x20000
#define IRQ2BIT         0x40000

#define UART0ID         0x2   /* UART 0 ISR Value = 2 */

#define US_INT_SETUP        0x0 /* Priority 0 SCRTYPE 0 - level sensitive */
#define INT_ALL_SRC     0x701FF /* All interrupt sources (int and ext) */

/* Power management control registers */
#define PMC_PCR     ((volatile int *) (AT91_PMC + 0x00)) /* Power control */

/* Watchdog timer registers */
#define WD_CONT1    ((volatile int *) (AT91_WDOG + 0x00)) /* Watchdog control */
#define WD_CONT2    ((volatile int *) (AT91_WDOG + 0x04)) /* Clock and counter */
#define WD_TIMEOUT  ((volatile int *) (AT91_WDOG + 0x08)) /* Reset timeout */
#define WD_STATUS   ((volatile int *) (AT91_WDOG + 0x0C)) /* Status */

typedef struct
{
  word lcr;
  word mcr;
  word ier;
  word idr;
  word imr;
  word csr;
  word rhr;
  word thr;
  word brg;
  word rtr;
  word ttr;
  word res;
  word rpr;
  word rcr;
  word tpr;
  word tcr;
}AT91RegsStruct;

#define AT91Serial ((volatile AT91RegsStruct *) AT91_SERA)


#define BOOTROMREG          0x0100012E /*0x01000000,16MB,8-bit, 3 wait states*/
#define FLASHREG            0x02000029 /*0x02000000,16MB,16-bit,3 wait states*/
#define CSR2DEF             0x03000129 /*0x03000000,16MB,16-bit,3 wait states*/
#define CSR3DEF             0x04000129 /*0x04000000,16MB,16-bit,3 wait states*/

#define MAP_SSRAM           0x00100000 /* SSRAM Base address */

#endif

/*****************************************************************************
 * $Log$
 *
 *
 *****************************************************************************/