hw.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

/*****************************************************************************
** Confidential
** Copyright (c) 1997 Advanced Risc Machines Limited
** All rights reserved
**
**      Filename : at91regs.h
**      Author   : Mark Snook
**      $Revision$
**
**  This file is under RCS control
**  RCS $Source$
**  $Id$
**
******************************************************************************
**   Purpose : Header file for AT91 Development Board test programs
**
**
**
******************************************************************************/

#ifndef __AT91REGS_H
#define __AT91REGS_H

/* some debug support for E5 ROM emulator */
#define E5BC_BASE       0x0000FFF0 /* Back channel base address */
#define E5BC_PCDATA ((volatile int *) (E5BC_BASE + 0x00)) /* unused, unused, bc_status, bc_pcdata */

/* base addresses */
#define AT91_MEM        0xFFE00000 /* Memory controller */
#define AT91_SERA   0xFFFD0000 /* Serial port A */
#define AT91_SERB   0xFFFCC000 /* Serial port B */
#define AT91_TIMER      0xFFFE0000 /* Counter/Timer module */
#define AT91_PIO        0xFFFF0000 /* Parallel I/O module */
#define AT91_PMC        0xFFFF4000 /* Power management controller */
#define AT91_WDOG       0xFFFF8000 /* Watchdog timer */
#define AT91_INT        0xFFFFF000 /* Interrupt controller */


/* Serial port registers */
#define SERA_LCR    ((volatile int *) (AT91_SERA + 0x00)) /* Port A Line control */
#define SERA_MCR    ((volatile int *) (AT91_SERA + 0x04)) /* Port A Mode control */
#define SERA_IER    ((volatile int *) (AT91_SERA + 0x08)) /* Port A Interrupt en register */
#define SERA_IDR    ((volatile int *) (AT91_SERA + 0x0C)) /* Port A Interrupt dis register */
#define SERA_IMR    ((volatile int *) (AT91_SERA + 0x10)) /* Port A Interrupt mask register */
#define SERA_CSR    ((volatile int *) (AT91_SERA + 0x14)) /* Port A Channel status */
#define SERA_RHR    ((volatile int *) (AT91_SERA + 0x18)) /* Port A Receive holding */
#define SERA_THR    ((volatile int *) (AT91_SERA + 0x1C)) /* Port A Transmit holding */
#define SERA_BRG    ((volatile int *) (AT91_SERA + 0x20)) /* Port A Baud rate divisor */
#define SERA_RTR    ((volatile int *) (AT91_SERA + 0x24)) /* Port A Receiver Time-out */
#define SERA_TTR    ((volatile int *) (AT91_SERA + 0x28)) /* Port A Transmitter Time-guard */
#define SERA_RPR    ((volatile int *) (AT91_SERA + 0x30)) /* Port A Receive pointer  */
#define SERA_RCR    ((volatile int *) (AT91_SERA + 0x34)) /* Port A Receive counter */
#define SERA_TPR    ((volatile int *) (AT91_SERA + 0x38)) /* Port A Transmit pointer  */
#define SERA_TCR    ((volatile int *) (AT91_SERA + 0x3C)) /* Port A Transmit counter */

#define SERB_LCR    ((volatile int *) (AT91_SERB + 0x00)) /* Port B Line control */
#define SERB_MCR    ((volatile int *) (AT91_SERB + 0x04)) /* Port B Mode control */
#define SERB_IER    ((volatile int *) (AT91_SERB + 0x08)) /* Port B Interrupt en register */
#define SERB_IDR    ((volatile int *) (AT91_SERB + 0x0C)) /* Port B Interrupt dis register */
#define SERB_IMR    ((volatile int *) (AT91_SERB + 0x10)) /* Port B Interrupt mask register */
#define SERB_CSR    ((volatile int *) (AT91_SERB + 0x14)) /* Port B Channel status */
#define SERB_RHR    ((volatile int *) (AT91_SERB + 0x18)) /* Port B Receive holding */
#define SERB_THR    ((volatile int *) (AT91_SERB + 0x1C)) /* Port B Transmit holding */
#define SERB_BRG    ((volatile int *) (AT91_SERB + 0x20)) /* Port B Baud rate divisor */
#define SERB_RTR    ((volatile int *) (AT91_SERB + 0x24)) /* Port B Receiver Time-out */
#define SERB_TTR    ((volatile int *) (AT91_SERB + 0x28)) /* Port B Transmitter Time-guard */
#define SERB_RPR    ((volatile int *) (AT91_SERB + 0x30)) /* Port B Receive pointer  */
#define SERB_RCR    ((volatile int *) (AT91_SERB + 0x34)) /* Port B Receive counter */
#define SERB_TPR    ((volatile int *) (AT91_SERB + 0x38)) /* Port B Transmit pointer  */
#define SERB_TCR    ((volatile int *) (AT91_SERB + 0x3C)) /* Port B Transmit counter */

/* LCR register bits */

#define RESETRX         0x0004
#define RESETTX         0x0008
#define ENABLERX        0x0010
#define DISABLERX       0x0020
#define ENABLETX        0x0040
#define DISABLETX       0x0080
#define RESETSTAT       0x0100
#define STARTBRK        0x0200
#define STOPBRK         0x0400
#define RTSON           0x0800 /* not implemented in AT91 */
#define RTSOFF          0x1000 /* not implemented in AT91 */
#define DTRON           0x2000 /* not implemented in AT91 */
#define DTROFF          0x4000 /* not implemented in AT91 */
#define READPARTDATA    0x8000

#define RESETERR         (RESETRX |  RESETTX | RESETSTAT)

/* MCR register bits */
#define INTCLK          0x0000
#define INTCLKDIV8      0x0010
#define EXTCLK          0x0020

#define CHAR5BIT        0x0000
#define CHAR6BIT        0x0040
#define CHAR7BIT        0x0080
#define CHAR8BIT        0x00C0

#define ASYNC           0x0000
//#define SYNC            0x0100

#define EVEN            0x0000
#define ODD             0x0200

#define PARITYENABLED   0x0000
#define FORCEPARITY     0x0400
#define NOPARITY        0x0800

#define STOP1BIT        0x0000
#define STOP15BIT       0x1000
#define STOP2BIT        0x2000

#define NORMAL          0x0000
#define AUTOECHO        0x4000
#define LOCALLOOPBACK   0x8000
#define REMOTELOOPBACK  0xC000

#define BYTEMODE        0x00000
#define HALFMODE        0x10000
#define WORDMODE        0x20000

#define BAUDRATEOUT     0x40000

/* IER/IDR/IMR register bits */
//#define RXRDY           0x0001  /* RX Ready Interrupt */
//#define TXRDY           0x0002  /* TX Ready Interrupt */
//#define RXBRK           0x0004  /* RX Break Interrupt */
//#define ENDRX           0x0008  /* End of RX Transfer Interrupt */
//#define ENDTX           0x0010  /* End of RX Transfer Interrupt */
//#define OVRE            0x0020  /* Overrun Error Interrupt */
//#define FRAME           0x0040  /* Framing Error Interrupt */
//#define PARE            0x0080  /* Parity Error Interrupt */
//#define TIMEOUT         0x0100  /* Timeout Interrupt */
//#define TXEMPTY         0x0200  /* TX Buffer Empty Interrupt */

/* CSR register bits */
#define RXDMA           0x0008  /* End of RX Transfer Interrupt */
#define TXDMA           0x0010  /* End of RX Transfer Interrupt */

#define NASTYERR        (OVRE | FRAME | PARE )

/* Baud Rate Generator values = MCLK / (16 * baud_val) */

/* Define the system frequency here - 4, 8, 16 or 32 (MHz) */

#ifndef SYS_FREQ
#define SYS_FREQ 16
#endif

//#define SYS_MCKI  32000000

#ifdef ___EB01
#define SYS_MCKI  32768000
#endif

#ifdef ___EB40
#define SYS_MCKI  32768000
#endif

#ifdef ___EB40A
#define SYS_MCKI  66000000
#endif

#ifdef ___EB42
#define SYS_MCKI    32768000
#endif

#ifdef ___EB55
#define SYS_MCKI    32000000
#endif

#ifdef ___EB63
#define SYS_MCKI    25000000
#endif

#ifdef  NEVER
#define BAUD_DEB        ((SYS_FREQ*1000000)/(16*1200))      /* Debug baud rate - 1200 */
#define BAUD_009        ((SYS_FREQ*1000000)/(16*9600))      /* 9600 baud rate */
#define BAUD_019        ((SYS_FREQ*1000000)/(16*19200))     /* 19200 baud rate */
#define BAUD_038        ((SYS_FREQ*1000000)/(16*38400))     /* 38400 baud rate */
#define BAUD_057        ((SYS_FREQ*1000000)/(16*57600))     /* 57600 baud rate */
#define BAUD_115        ((SYS_FREQ*1000000)/(16*115200))    /* 115200 baud rate */
#endif

#define BAUD_DEB        (SYS_MCKI/(16*1200))        /* Debug baud rate - 1200 */
#define BAUD_009        (SYS_MCKI/(16*9600))        /* 9600 baud rate */
#define BAUD_019        (SYS_MCKI/(16*19200))       /* 19200 baud rate */
#define BAUD_038        (SYS_MCKI/(16*38400))       /* 38400 baud rate */
#define BAUD_057        (SYS_MCKI/(16*57600))       /* 57600 baud rate */
#define BAUD_115        (SYS_MCKI/(16*115200))      /* 115200 baud rate */

#ifdef  NEVER
#   if SYS_FREQ == 4  /* 4 MHz Option */

#define BAUD_DEB       208   /* Debug baud rate - 1200 */
#define BAUD_009        26   /* 9600 baud rate */
#define BAUD_019        13   /* 19200 baud rate */
#define BAUD_038         7   /* 38400 baud rate */
#define BAUD_057         4   /* 57600 baud rate */
#define BAUD_115         2   /* 115200 baud rate */

#   elif SYS_FREQ == 8  /* 8 MHz Option */

#define BAUD_DEB       417   /* Debug baud rate - 1200 */
#define BAUD_009        52   /* 9600 baud rate */
#define BAUD_019        26   /* 19200 baud rate */
#define BAUD_038        13   /* 38400 baud rate */
#define BAUD_057         9   /* 57600 baud rate */
#define BAUD_115         4   /* 115200 baud rate */

#   elif SYS_FREQ == 16  /* 16 MHz Option */

#define BAUD_DEB       833   /* Debug baud rate - 1200 */
#define BAUD_009       104   /* 9600 baud rate */
#define BAUD_019        52   /* 19200 baud rate */
#define BAUD_038        26   /* 38400 baud rate */
#define BAUD_057        17   /* 57600 baud rate */
#define BAUD_115         9   /* 115200 baud rate */

#   else  /* default and 32 MHz option */

#define BAUD_DEB      1667   /* Debug baud rate - 1200 */
#define BAUD_009       208   /* 9600 baud rate */
#define BAUD_019       104   /* 19200 baud rate */
#define BAUD_038        52   /* 38400 baud rate */
#define BAUD_057        35   /* 57600 baud rate */
#define BAUD_115        17   /* 115200 baud rate */