irq_pio.paf.arm

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

#line 1

#line 2

#line 3

#line 4

#line 5

#line 6

#line 7

#line 8

#line 9

#line 10

#line 11

#line 12

#line 13

#line 14

#line 15

#line 16
;.section ".Irq","ax" 
;.Irq
#line 17
#line 17

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
#define AIC_PRIOR                            0x07    
#line 18

#line 18
#define AIC_SRCTYPE                          0x60    
#line 18
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE      0x00    
#line 18
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED       0x20    
#line 18
#define AIC_SRCTYPE_EXT_LOW_LEVEL            0x00    
#line 18
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE        0x20    
#line 18
#define AIC_SRCTYPE_EXT_HIGH_LEVEL           0x40    
#line 18
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE        0x60    
#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
#define AIC_IRQID                    0x1F            
#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
#define AIC_NFIQ                     0x01            
#line 18
#define AIC_NIRQ                     0x02            
#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
#define AIC_BASE                     0xFFFFF000
#line 18

#line 18
	/*END*/
#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
#define ARM_MODE_USER                0x10
#line 18
#define ARM_MODE_FIQ                 0x11
#line 18
#define ARM_MODE_IRQ                 0x12
#line 18
#define ARM_MODE_SVC                 0x13
#line 18
#define ARM_MODE_ABORT               0x17
#line 18
#define ARM_MODE_UNDEF               0x1B
#line 18
#define ARM_MODE_SYS                 0x1F
#line 18

#line 18
#define I_BIT                        0x80
#line 18
#define F_BIT                        0x40
#line 18
#define T_BIT                        0x20
#line 18

#line 18
            /*END*/
#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18

#line 18
            /*END*/
#line 18

#line 18
#line 19
#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19

#line 19
                /*END*/
#line 19

#line 19
#line 20
#line 20
	    
#line 21

#line 22

#line 23

#line 24

#line 25

#line 26

#line 27
            IMPORT      pio_c_irq_handler
#line 28
            EXPORT      pio_asm_irq_handler
#line 29
pio_asm_irq_handler
#line 30

#line 31

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32
            sub         r14, r14, 4
#line 32
#line 32
#line 32
            stmfd       sp!, {r14}
#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32
            ldr         r14, =AIC_BASE
#line 32
#line 32
#line 32
            str         r14, [r14, 0x100]
#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32
            mrs         r14, SPSR
#line 32
#line 32
#line 32
            stmfd       sp!, {r0, r14}
#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32
            mrs         r0, CPSR
#line 32
#line 32
#line 32
            bic         r0, r0, I_BIT
#line 32
#line 32
#line 32
            orr         r0, r0, ARM_MODE_SYS
#line 32
#line 32
#line 32
            msr         CPSR_c, r0
#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 32
#line 32
#line 32
            #if 1;  "" == ""
#line 32
#line 32
#line 32
            stmfd       sp!, { r1-r3, r12, r14}
#line 32
#line 32
#line 32
            #else
#line 32
#line 32
#line 32
            stmfd       sp!, { r1-r3, , r12, r14}
#line 32
#line 32
#line 32
            #endif
#line 32
#line 32
#line 32

#line 32
#line 32
#line 32

#line 33

#line 34
            ldr         r0, =pio_c_irq_handler
#line 35
            mov         r14, pc
#line 36
            bx          r0
#line 37

#line 38
	    b		exit_irq
#line 39

#line 40

#line 41

#line 42

#line 43

#line 44

#line 45

#line 46
            EXPORT      irq0_asm_irq_handler
#line 47
            IMPORT      at91_IRQ0_handler
#line 48
irq0_asm_irq_handler
#line 49

#line 50

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51
            sub         r14, r14, 4
#line 51
#line 51
#line 51
            stmfd       sp!, {r14}
#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51
            ldr         r14, =AIC_BASE
#line 51
#line 51
#line 51
            str         r14, [r14, 0x100]
#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51
            mrs         r14, SPSR
#line 51
#line 51
#line 51
            stmfd       sp!, {r0, r14}
#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51
            mrs         r0, CPSR
#line 51
#line 51
#line 51
            bic         r0, r0, I_BIT
#line 51
#line 51
#line 51
            orr         r0, r0, ARM_MODE_SYS
#line 51
#line 51
#line 51
            msr         CPSR_c, r0
#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 51
#line 51
#line 51
            #if 1;  "" == ""
#line 51
#line 51
#line 51
            stmfd       sp!, { r1-r3, r12, r14}
#line 51
#line 51
#line 51
            #else
#line 51
#line 51
#line 51
            stmfd       sp!, { r1-r3, , r12, r14}
#line 51
#line 51
#line 51
            #endif
#line 51
#line 51
#line 51

#line 51
#line 51
#line 51

#line 52

#line 53
            ldr         r0, =at91_IRQ0_handler
#line 54
            mov         r14, pc
#line 55
            bx          r0
#line 56

#line 57
	    b		exit_irq
#line 58

#line 59

#line 60

#line 61

#line 62

#line 63

#line 64

#line 65
            EXPORT      sw_asm_irq_handler
#line 66
            IMPORT      aic_sotfware_interrupt
#line 67
sw_asm_irq_handler
#line 68

#line 69

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70
            sub         r14, r14, 4
#line 70
#line 70
#line 70
            stmfd       sp!, {r14}
#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70
            ldr         r14, =AIC_BASE
#line 70
#line 70
#line 70
            str         r14, [r14, 0x100]
#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70
            mrs         r14, SPSR
#line 70
#line 70
#line 70
            stmfd       sp!, {r0, r14}
#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70
            mrs         r0, CPSR
#line 70
#line 70
#line 70
            bic         r0, r0, I_BIT
#line 70
#line 70
#line 70
            orr         r0, r0, ARM_MODE_SYS
#line 70
#line 70
#line 70
            msr         CPSR_c, r0
#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 70
#line 70
#line 70
            #if 1;  "" == ""
#line 70
#line 70
#line 70
            stmfd       sp!, { r1-r3, r12, r14}
#line 70
#line 70
#line 70
            #else
#line 70
#line 70
#line 70
            stmfd       sp!, { r1-r3, , r12, r14}
#line 70
#line 70
#line 70
            #endif
#line 70
#line 70
#line 70

#line 70
#line 70
#line 70

#line 71

#line 72
            ldr         r0, =aic_sotfware_interrupt
#line 73
            mov         r14, pc
#line 74
            bx          r0
#line 75

#line 76
exit_irq
#line 77

#line 78
#line 78
#line 78
   
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78
            #if 1;  "" == ""
#line 78
#line 78
#line 78
            ldmia       sp!, { r1-r3, r12, r14}
#line 78
#line 78
#line 78
            #else
#line 78
#line 78
#line 78
            ldmia       sp!, { r1-r3, , r12, r14}
#line 78
#line 78
#line 78
            #endif
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78

#line 78
#line 78
#line 78
            mrs         r0, CPSR
#line 78
#line 78
#line 78
            bic         r0, r0, ARM_MODE_SYS
#line 78
#line 78
#line 78
            orr         r0, r0, I_BIT | ARM_MODE_IRQ
#line 78
#line 78
#line 78
            msr         CPSR_c, r0
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78

#line 78
#line 78
#line 78
            ldr         r0, =AIC_BASE
#line 78
#line 78
#line 78
            str         r0, [r0, 0x130]
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78

#line 78
#line 78
#line 78
            ldmia       sp!, {r0, r14}
#line 78
#line 78
#line 78
            msr         SPSR_cxsf, r14
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78

#line 78
#line 78
#line 78
            ldmia       sp!, {pc}^
#line 78
#line 78
#line 78

#line 78
#line 78
#line 78

#line 79
	    
#line 80

#line 81

#line 82

#line 83

#line 84

#line 85

#line 86
           EXPORT      asm_fiq_init_handler
#line 87

#line 88
asm_fiq_init_handler
#line 89

#line 90

#line 91
            sub         r14, r14, 4
#line 92
            stmfd       sp!, {r14}
#line 93
            ldr         r12, =AIC_BASE
#line 94

#line 95
            str         r12, [r12, 0x100]
#line 96

#line 97

#line 98

#line 99
            ldmia       sp!, {pc}^
#line 100

#line 101

#line 102

#line 103

#line 104

#line 105

#line 106

#line 107
           EXPORT      asm_fiq_handler
#line 108
           IMPORT      FIQ_handler
#line 109
            
#line 110

#line 111
asm_fiq_handler
#line 112
		
#line 113

#line 114
            sub         r14, r14, 4
#line 115
            stmfd       sp!, {r14}
#line 116

#line 117

#line 118

#line 119
            str         r12, [r12, 0x100]
#line 120

#line 121

#line 122
            mrs         r14, SPSR
#line 123
            stmfd       sp!, {r0, r14}
#line 124

#line 125

#line 126
            mrs         r0, CPSR
#line 127
            bic         r0, r0, F_BIT
#line 128
            orr         r0, r0, ARM_MODE_SYS
#line 129
            msr         CPSR_c, r0			
#line 130
            stmfd       sp!, { r1-r3, r12, r14}
#line 131

#line 132

#line 133
            ldr		r0, =FIQ_handler
#line 134
            mov         r14, pc
#line 135
            bx          r0           
#line 136

#line 137

#line 138
            ldmia       sp!, { r1-r3, r12, r14}
#line 139

#line 140
            mrs         r0, CPSR
#line 141
            bic         r0, r0, ARM_MODE_SYS
#line 142
            orr         r0, r0, F_BIT | ARM_MODE_FIQ
#line 143
            msr         CPSR_c, r0			
#line 144

#line 145

#line 146

#line 147

#line 148
            ldmia       sp!, {r0, r14}
#line 149
            msr         SPSR_cxsf, r14
#line 150

#line 151

#line 152
            ldmia       sp!, {pc}^
#line 153

#line 154
            /*END*/
#line 155