cstartup_meta.s

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source          : cstartup_ice_meta.s
;- Object               : Boot for Final Application version to be loaded in SRAM.
;-
;- 1.0 16/01/01 JPP     : Creation Metaware
;- 1.1 12/09/01 JPP		: Modification for bench
;------------------------------------------------------------------------------

                include     eb40_meta.inc

;- you must be iclude the part of metaware initialisation

;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at SRAM.
; All AT91 microcontroler in reset sate ARM 32 bit
;------------------------------------------------------------------------------
   	.option code32
	.text
	.global _start
	.type	_start,@function
	.weak	_0			; dummy symbol to allow relative addr
	.weak	sp$$stack$$Base
	ENTRY



;------------------------------------------------------------------------------
;- Exception vectors
;--------------------
;- These vectors are read at address 0 before remap. for Flash and the RAM address
;- for ICE or Angel
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;- After Remap, these vectors are mapped at address 0x100 0000 and only a
;- reset (internal or external) can make of them the actual ARM vectors.
;- Note that the infinite loop has advantage that a debugger can to show up
;- very quickly an hardware issue during the boot sequence.
;------------------------------------------------------------------------------
Reset:
                B           InitReset       ; reset
undefvec:
                B           undefvec        ; Undefined Instruction
swivec:
                B           swivec          ; Software Interrupt
pabtvec:
                B           pabtvec         ; Prefetch Abort
dabtvec:
                B           dabtvec         ; Data Abort
rsvdvec:
                B           rsvdvec         ; reserved
irqvec:
                B           irqvec          ; reserved
fiqvec:
                B           fiqvec          ; reserved

;------------------------------------------------------------------------------
;- Exception vectors ( after cstartup execution )
;------------------------------------
;- These vectors are read at RAM address after the remap command is performed in
;- the EBI. As they will be relocated at address 0x0 to be effective, a
;- relative addressing is forbidden. The only possibility to get an absolute
;- addressing for an ARM vector is to read a PC relative value at a defined
;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
;- vectors) for storing the absolute exception handler address.
;- The AIC vectoring access vectors are saved in the interrupt and fast
;- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
;- offset is never used).
;- The provisory handler addresses are defined on infinite loop and can be
;- modified at any time.
;- Note also that the reset is only accessible by a jump from the application
;- to 0. It is an actual software reset.
;- As the 13 first location are used by the vectors, the read/write link
;- address must be defined from 0x34 if internal data mapping is required.
;- (use for that the option -rw- base=0x34
;------------------------------------------------------------------------------
VectorTable:
                ldr         pc, [pc, #18]          ; SoftReset
                ldr         pc, [pc, #18]          ; UndefHandler
                ldr         pc, [pc, #18]          ; SWIHandler
                ldr         pc, [pc, #18]          ; PrefetchAbortHandler
                ldr         pc, [pc, #18]          ; DataAbortHandler
                nop                                ; Reserved
                ldr         pc, [pc,#-0xF20]       ; IRQ : read the AIC
                ldr         pc, [pc,#-0xF20]       ; FIQ : read the AIC

;- There are only 5 offsets as the vectoring is used.
                DCD         SoftReset
                DCD         UndefHandler
                DCD         SWIHandler
                DCD         PrefetchAbortHandler
                DCD         DataAbortHandler
;- Vectoring Execution function run at absolut addresss
SoftReset:
                b           SoftReset
UndefHandler:
                b           UndefHandler
SWIHandler:
                b           SWIHandler
PrefetchAbortHandler:
                b           PrefetchAbortHandler
DataAbortHandler:
                b           DataAbortHandler

;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------
;- The EBI values depend to target choice , Clock, and memories access time.
;- Yous must be define these values in include file
;- The EBI User Interface Image which is copied by the boot.
;- The EBI_CSR_x are defined in the target and hardware depend.
;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
;- EBI Base Address is added at the end for commodity in copy code.
;- ICE note :For ICE debug no need to set the EBI value these values already set
;- by the boot function.
;------------------------------------------------------------------------------
InitTableEBI:
            DCD         EBI_CSR_0
            DCD         EBI_CSR_1
            DCD         EBI_CSR_2
            DCD         EBI_CSR_3
            DCD         EBI_CSR_4
            DCD         EBI_CSR_5
            DCD         EBI_CSR_6
            DCD         EBI_CSR_7
            DCD         0x00000001  ; REMAP command
            DCD         0x00000006  ; 6 memory regions, standard read
PtEBIBase:
            DCD         EBI_BASE    ; EBI Base Address

;------------------------------------------------------------------------------
;- The reset handler before Remap
;--------------------------------
;- From here, the code is executed from SRAM address
;------------------------------------------------------------------------------
InitReset:

			.ifdef	AT91_DEBUG_ANGEL    ; use
;----------------------------------------------------------------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
;----------------------------------------------------------------------

                bl      __low_level_init

;------------------------------------------------------------------------------
;- Initialise the Memory Controller
;----------------------------------
;- The IniTableEBI addressing must be relative .
;- The PtInitRemap must be absolute as the processor jumps at this address
;- Note also that the EBI base address is loaded in r11 by the "ldmia".
;------------------------------------------------------------------------------
;- Copy the Image of the Memory Controller
                sub     r10, pc,#(8+.-InitTableEBI) ; get the address of the chip select register image
;- Copy Chip Select Register Image to Memory Controller and command remap
                ldmia   r10!, {r0-r9,r11}       ; load the complete image and the EBI base
                stmia   r11!, {r0-r9}           ; store the complete image with the remap command
			.else 								; AT91_DEBUG_ANGEL
;- Flag only for AT91_DEBUG_ICE AT91_DEBUG_NONE
;------------------------------------------------------------------------------
;- Speed up the Boot sequence
;----------------------------
;- After reset, the number os wait states on chip select 0 is 8. All AT91
;- Evaluation Boards fits fast flash memories, so that the number of wait
;- states can be optimized to fast up the boot sequence.
;- ICE note :For ICE debug no need to set the EBI value these values already set
;- by the boot function.
;------------------------------------------------------------------------------
;- Load System EBI Base address and CSR0 Init Value
                ldr     r0, PtEBIBase
                ldr     r1, [pc,#-(8+.-InitTableEBI)] ; values (relative)

;- Speed up code execution by disabling wait state on Chip Select 0
                str     r1, [r0]

;------------------------------------------------------------------------------
;- low level init
;----------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
;----------------------------------------------------------------------

                bl      __low_level_init

;------------------------------------------------------------------------------
;- Reset the Interrupt Controller
;--------------------------------
;- Normally, the code is executed only if a reset has been actually performed.
;- So, the AIC initialization resumes at setting up the default vectors.
;------------------------------------------------------------------------------
;- Load the AIC Base Address and the default handler addresses
                add     r0, pc,AicData-8-. ; @ where to read values (relative)

                ldmia   r0, {r1-r4}