cstartup_ice.arm

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

                subs        r0, r0, #1
                bhi         LoopAic0

;- Set up the default interrupt handler vectors
                str     r2, [r1, #AIC_SVR]      ; SVR[0] for FIQ
                add     r1, r1, #AIC_SVR
                mov     r0, #31                 ; counter
LoopAic1:
                str     r3, [r1, r0, LSL #2]    ; SVRs for IRQs
                subs    r0, r0, #1              ; do not save FIQ
                bhi     LoopAic1

                b       EndInitAic

;------------------------------------------------------------------------------
;- Default Interrupt Handler
;---------------------------
;- These function are defined in the AT91 library. If you want to change this
;- you can redifine these function in your appication code
;------------------------------------------------------------------------------
;- Default Interrupt Handlers
AicData:
    .data.w         AIC_BASE        ; AIC Base Address

                IMPORT  at91_default_fiq_handler
                IMPORT  at91_default_irq_handler
                IMPORT  at91_spurious_handler
PtDefaultHandler
        .data.w     at91_default_fiq_handler
        .data.w     at91_default_irq_handler
        .data.w     at91_spurious_handler
EndInitAic:

;------------------------------------------------------------------------------
;- Setup Exception Vectors in Internal RAM before Remap
;------------------------------------------------------
;- That's important to perform this operation before Remap in order to guarantee
;- that the core has valid vectors at any time during the remap operation.
;- Note: There are only 5 offsets as the vectoring is used.
;- ICE note : In this code only the start address value is changed if you use
;- without Semihosting.
;-  Before Remap the internal RAM it's 0x300000
;-  After  Remap the internal RAM it's 0x000000
;-      Remap it's already executed it's no possible to write to 0x300000.
;------------------------------------------------------------------------------
;- Copy the ARM exception vectors

; The RAM_BASE = 0 it's specific for ICE
                mov     r8,#RAM_BASE            ; @ of the hard vector after remap  in internal RAM 0x0

                sub     r9, pc,8+.-VectorTable  ; @ where to read values (relative)
                ldmia   r9!, {r0-r7}            ; read 8 vectors
                stmia   r8!, {r0-r7}            ; store them

                ldmia   r9!, {r0-r4}            ; read 5 absolute handler addresses
                stmia   r8!, {r0-r4}            ; store them

;------------------------------------------------------------------------------
;- Initialise the Memory Controller
;----------------------------------
;- That's principaly the Remap Command. Actually, all the External Bus
;- Interface is configured with some instructions and the User Interface Image
;- as described above. The jump "mov pc, r12" could be unread as it is after
;- located after the Remap but actually it is thanks to the Arm core pipeline.
;- The IniTableEBI addressing must be relative .
;- The PtInitRemap must be absolute as the processor jumps at this address
;- immediatly after the Remap is performed.
;- Note also that the EBI base address is loaded in r11 by the "ldmia".
;- ICE note :For ICE debug these values already set by the boot function and the
;- Remap it's already executed it's no need to set still.
;------------------------------------------------------------------------------


;- Copy the Image of the Memory Controller
                add     r10, pc,ImageMemorySelect-8-.  ; @ where to read values (relative)
                                                     ; get the address of the chip select register image

;- Copy Chip Select Register Image to Memory Controller and command remap
                ldmia   r10!, {r0-r9,r11-r12}      ; load the complete image and the EBI base
                stmia   r11!, {r0-r9}           ; store the complete image with the remap command

;- Jump to ROM at its new address
                mov     pc, r12                 ; jump and break the pipeline


.type _ghs_board_init,$function
.size _ghs_board_init,.-_ghs_board_init

;------------------------------------------------------------------------------
;- The Reset Handler after Remap
;-------------------------------
;- From here, the code is continous execute from its link address.
;------------------------------------------------------------------------------
_begin::
; *****************************************************************************

;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 3 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt is the same than Interrupt without priority level.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------

#define     IRQ_STACK_SIZE      (3*8*4)     /* 3 words per interrupt priority level */
#define     FIQ_STACK_SIZE      (3*4)       /* 3 words                              */
#define     ABT_STACK_SIZE      (1*4)       /* 1 word                               */
#define     UND_STACK_SIZE      (1*4)       /* 1 word                               */

;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Fast Interrupt, Interrupt, Abort, Undefined and Supervisor Stack are located
;- at the top of internal memory in order to speed the exception handling
;- context saving and restoring.
;- User (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------

#define     TOP_EXCEPTION_STACK    0x2000 /* RAM_LIMIT      Defined in part */
;TOP_APPLICATION_STACK   EXT_SRAM_LIMIT     /* Defined in Target */

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
                ldr     r0, =TOP_EXCEPTION_STACK

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
                msr     CPSR_cxsf, #ARM_MODE_FIQ | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack FIQ
                sub     r0, r0, #FIQ_STACK_SIZE

;- Set up Interrupt Mode and set IRQ Mode Stack
                msr     CPSR_cxsf, #ARM_MODE_IRQ | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack IRQ
                sub     r0, r0, #IRQ_STACK_SIZE

;- Set up Abort Mode and set Abort Mode Stack
                msr     CPSR_cxsf, #ARM_MODE_ABORT | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack Abort
                sub     r0, r0, #ABT_STACK_SIZE

;- Set up Undefined Instruction Mode and set Undef Mode Stack
                msr     CPSR_cxsf, #ARM_MODE_UNDEF | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack Undef
                sub     r0, r0, #UND_STACK_SIZE

;- Set up Supervisor Mode and set Supervisor Mode Stack
                msr     CPSR_cxsf, #ARM_MODE_SVC | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack Sup


 ;- Clear BSS (zero init)
 ;- ----------------------
 .weak __ghsbegin_bss
 .weak __ghsend_bss

                ldr         r1, =__ghsend_bss     ; Get pointer to top of BSS
                ldr         r3, =__ghsbegin_bss   ; Bottom of BSS
                mov         r2, 0
 LoopZI:
                cmp         r3, r1
                strcc       r2, [r3], 4
                bcc         LoopZI

 ;- Clear SBSS (zero init)
 ;- ----------------------
 .weak __ghsbegin_sbss
 .weak __ghsend_sbss

                ldr         r1, =__ghsend_sbss    ; Get pointer to top of SBSS
                ldr         r3, =__ghsbegin_sbss  ; Bottom of SBSS
                mov         r2, 0
 LoopZI2:
                cmp         r3, r1
                strcc       r2, [r3], 4
                bcc         LoopZI2


;------------------------------------------------------------------------------
;- Setup Application Operating Mode and Enable the interrupts
;------------------------------------------------------------
;- System Mode is selected first and the stack is setup. This allows to prevent
;- any interrupt occurence while the User is not initialized. System Mode is
;- used as the interrupt enabling would be avoided from User Mode (CPSR cannot
;- be written while the core is in User Mode).
;------------------------------------------------------------------------------
                msr     CPSR_c, #ARM_MODE_USER      ; set User mode
                ldr     R13, =__ghsend_stack
;- intialise the heap
                ldr     r12, =__ghsbegin_heap   ; Get pointer to top of romdata

;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors
;------------------------------------------------------------------------------
                ldr         r0, =main
                mov         lr, pc
                bx          r0                  ; Go main

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End:
                b           End

.type _ghs_board_init,$function
.size _ghs_board_init,.-_ghs_board_init

;----------------------------------------------------------------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
; Enable all peripherial clock
; The peripheral clocks are automatically enabled after a reset.
;----------------------------------------------------------------------
__low_level_init:
                mvn         r0,#0               ; R0<- 0xFFFFFFFF
                ldr         r1,=PS_BASE         ; Get Power saving configuartion
                str         r0,[r1, #PS_PCER]   ; Enable all peripherial clock
                mov         pc,r14              ; Return
.type __low_level_init,$function
.size __low_level_init,.-__low_level_init

; ***************************************************************************
; * This is data used to setup the boards memory
PtImageMemorySelect:
    .data.w         ImageMemorySelect
;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------
;- The EBI values depend to target choice , Clock, and memories access time.
;- Yous must be define these values in include file
;- The EBI User Interface Image which is copied by the boot.
;- The EBI_CSR_x are defined in the target and hardware depend.
;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
;- EBI Base Address is added at the end for commodity in copy code.
;- ICE note :For ICE debug no need to set the EBI value these values already set
;- by the boot function.
;------------------------------------------------------------------------------

ImageMemorySelect:
    .data.w         0x01002529  ; 0x01000000, 16MB,  2 cycles added after transfer, 16-bit, 6 wait states
    .data.w         0x02002121  ; 0x02000000, 16MB,  0 cycles added after transfer, 16-bit, 1 wait state
    .data.w         0x20000000  ; unused
    .data.w         0x30000000  ; unused
    .data.w         0x40000000  ; unused
    .data.w         0x50000000  ; unused
    .data.w         0x60000000  ; unused
    .data.w         0x70000000  ; unused
    .data.w         0x00000001  ; REMAP commande
    .data.w         0x00000006  ; 7 memory regions, standard read
EBI_base_address:
    .data.w         AT91_EBI    ; EBI address
    .data.w         _begin      ; Start of high level initialization

PtVectorInit:
    .data.w         _ghs_board_init     ; begining of vector table