cstartup_ice.arm

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source          : cstartup_ice.arm
;- Object               : Boot for Final Application version to be loaded in SRAM.
;-
;- 1.0 07/09/01 JPP    : Creation Green Hills Version 3.01
;------------------------------------------------------------------------------


#define RAM_BASE    0x0

;------------------------------------------
;- AIC User Interface Structure Definition
;------------------------------------------
#define         AIC_SMR     0x000       /*- Source Mode Register                -*/
#define         AIC_SVR     0x080       /*- Source Vector Register              -*/
#define         AIC_IVR     0x100       /*- IRQ Vector Register                 -*/
#define         AIC_FVR     0x104       /*- FIQ Vector Register                 -*/
#define         AIC_ISR     0x108       /*- Interrupt Status Register           -*/
#define         AIC_IPR     0x10c       /*- Interrupt Pending Register          -*/
#define         AIC_IMR     0x110       /*- Interrupt Mask Register             -*/
#define         AIC_CISR    0x114       /*- Core Interrupt Status Register      -*/
                                        /*- Reserved                            -*/
#define         AIC_IECR    0x120       /*- Interrupt Enable Command Register   -*/
#define         AIC_IDCR    0x124       /*- Interrupt Disable Command Register  -*/
#define         AIC_ICCR    0x128       /*- Interrupt Clear Command Register    -*/
#define         AIC_ISCR    0x12c       /*- Interrupt Set Command Register      -*/
#define         AIC_EOICR   0x130       /*-  of Interrupt Command Register      -*/
#define         AIC_SPU     0x134       /*- Spurious Vector Register  0         -*/

;---------------------------------------------
;- AIC_SMR[]: Interrupt Source Mode Registers
;---------------------------------------------
#define         AIC_PRIOR                           0x07    /*- Priority        -*/

#define         AIC_SRCTYPE                         0x60    /*- Source Type Definition -*/
#define         AIC_SRCTYPE_INT_LEVEL_SENSITIVE     0x00    /*- Level Sensitive -*/
#define         AIC_SRCTYPE_INT_EDGE_TRIGGERED      0x20    /*- Edge Triggered  -*/
#define         AIC_SRCTYPE_EXT_LOW_LEVEL           0x00    /*- Low Level       -*/
#define         AIC_SRCTYPE_EXT_NEGATIVE_EDGE       0x20    /*- Negative Edge   -*/
#define         AIC_SRCTYPE_EXT_HIGH_LEVEL          0x40    /*- High Level      -*/
#define         AIC_SRCTYPE_EXT_POSITIVE_EDGE       0x60    /*- Positive Edge   -*/

;--------------------------------------
;-  AIC_ISR: Interrupt Status Register
;--------------------------------------
#define         AIC_IRQID            0x1F            /*- Current source interrupt  -*/

;-------------------------------------------
;- AIC_CISR: Interrupt Core Status Register
;-------------------------------------------
#define         AIC_NFIQ             0x01            /*- Core FIQ Status  -*/
#define         AIC_NIRQ             0x02            /*- Core IRQ Status  -*/

;--------------------------------------------
;- Advanced Interrupt COntroller BAse Address
;--------------------------------------------
#define         AIC_BASE            0xFFFFF000



/* These are just a few useful values */

#define     ARM_MODE_USER   0x10
#define     ARM_MODE_FIQ    0x11
#define     ARM_MODE_IRQ    0x12
#define     ARM_MODE_SVC    0x13
#define     ARM_MODE_ABORT  0x17
#define     ARM_MODE_UNDEF  0x1B
#define     ARM_MODE_SYS    0x1F

#define     I_BIT           0x80
#define     F_BIT           0x40
#define     T_BIT           0x20

#define     AT91_EBI        0xFFE00000      ; Memory controller


#define 	PS_CR          0x000  		/* Control Register	*/
#define 	PS_PCER        0x004  		/* Peripheral Clock Enable Register */
#define 	PS_PCDR        0x008  		/* Peripheral Clock Disable Register*/
#define 	PS_PCSR        0x00C  		/* Peripheral Clock Status Register	*/


#define     PS_BASE         0xFFFF4000

;------------------------------------------------------------------------------
;-      The AT91 microcontrolers starts execution at 0x00000000, which is
;- flash upon a reboot or power-up.  We will imediately re-map flash to CS0
;- (for Evaluation board 0x010000000 and begin executing at "InitReset".
;-  this code at 0x1000000.
;-    In order for the elf executable file to start execution from
;-  _ghs_board_init, you will need to specify the starting address with-in the
;-  MULTI Builder or on the linker command line.
;-    To to this in MULTI 2000 Builder, right mouse click on your program
;-  build file and select the menu item "File Options...".  This will open a
;-  tabbed dialog.  Select the "Advanced" tab and specify the starting address
;-  in the "start address:" text box.  The start address can be any global
;-  symbol.
;-     See the "Arm Embedded Development Guide" for direction on how to set
;-  the starting address on the linker command line.
;------------------------------------------------------------------------------


;------------------------------------------------------------------------------
;- Define the entry point
;------------------------
;- Note on the link address and the Remap command.
;- In order to guarantee that the non position-independant code (the ARM linker
;- armlink doesn't generate position-independant code) can work on the ARM,
;- it must be linked at address at which it expects to run.
;- In this startup example, we use RAM as base address.
;------------------------------------------------------------------------------

;------------------------------------------------------------------------------
;-  _ghs_board_init, you will need to specify the starting address with-in the
;-  MULTI Builder or on the linker command line.
;-     To to this in MULTI 2000 Builder, right mouse click on your program
;-  build file and select the menu item "File Options...".  This will open a
;-  tabbed dialog.  Select the "Advanced" tab and specify the starting address
;-  in the "start address:" text box.  The start address can be any global
;-  symbol.
;-     See the "Arm Embedded Development Guide" for direction on how to set
;-  the starting address on the linker command line.
;------------------------------------------------------------------------------
__main::

_ghs_board_init::

;------------------------------------------------------------------------------
;- Exception vectors
;--------------------
;- In the ICE function your board as run the boot code and initialize the remap
;- feature. but these code it's location independant and can be emulate the csartup_fash
;- fonctionnality.
;- These vectors are read at RAM address. in Flash mode these vectors are at 0
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;------------------------------------------------------------------------------
                B           InitReset       ; reset
undefvec:
                B           undefvec        ; Undefined Instruction
swivec:
                B           swivec          ; Software Interrupt
pabtvec:
                B           pabtvec         ; Prefetch Abort
dabtvec:
                B           dabtvec         ; Data Abort
rsvdvec:
                B           rsvdvec         ; reserved
irqvec:
                B           irqvec          ; reserved
fiqvec:
                B           fiqvec          ; reserved


;------------------------------------------------------------------------------
;- Exception vectors ( after cstartup execution )
;------------------------------------
;- These vectors are read at RAM address after the remap command is performed in
;- the EBI. As they will be relocated at address 0x0 to be effective, a
;- relative addressing is forbidden. The only possibility to get an absolute
;- addressing for an ARM vector is to read a PC relative value at a defined
;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
;- vectors) for storing the absolute exception handler address.
;- The AIC vectoring access vectors are saved in the interrupt and fast
;- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
;- offset is never used).
;- The provisory handler addresses are defined on infinite loop and can be
;- modified at any time.
;- Note also that the reset is only accessible by a jump from the application
;- to 0. It is an actual software reset.
;- As the 13 first location are used by the vectors, the read/write link
;- address must be defined from 0x34 if internal data mapping is required.
;- (use for that the option -rw- base=0x34
;------------------------------------------------------------------------------
VectorTable

                ldr         pc, [pc, 0x18]          ; SoftReset
                ldr         pc, [pc, 0x18]          ; UndefHandler
                ldr         pc, [pc, 0x18]          ; SWIHandler
                ldr         pc, [pc, 0x18]          ; PrefetchAbortHandler
                ldr         pc, [pc, 0x18]          ; DataAbortHandler
                nop                                 ; Reserved
                ldr         pc, [pc,-0xF20]         ; IRQ : read the AIC
                ldr         pc, [pc,-0xF20]         ; FIQ : read the AIC

;- There are only 5 offsets as the vectoring is used.
ImageMemoryVectoring:
                .data.w     SoftReset
                .data.w     UndefHandler
                .data.w     SWIHandler
                .data.w     PrefetchAbortHandler
                .data.w     DataAbortHandler

;- Vectoring Execution function run at absolut addresss
SoftReset:
                b           SoftReset
UndefHandler:
                b           UndefHandler
SWIHandler:
                b           SWIHandler
PrefetchAbortHandler:
                b           PrefetchAbortHandler
DataAbortHandler:
                b           DataAbortHandler


;------------------------------------------------------------------------------
;- The reset handler before Remap
;--------------------------------
;- From here, the code is executed from SRAM address
;------------------------------------------------------------------------------
InitReset:

;------------------------------------------------------------------------------
;- Speed up the Boot sequence
;----------------------------
;- After reset, the number os wait states on chip select 0 is 8. All AT91
;- Evaluation Boards fits fast flash memories, so that the number of wait
;- states can be optimized to fast up the boot sequence.
;- ICE note :For ICE debug no need to set the EBI value these values already set
;- by the boot function.
;------------------------------------------------------------------------------
;- Load System EBI Base address and CSR0 Init Value
                add     r0, pc,EBI_base_address-8-.  ; @ where to read values (relative)
                ldr     r0,[r0]
                add     r1, pc,ImageMemorySelect-8-.  ; @ where to read values (relative)
                ldr     r1,[r1]
;- Speed up code execution by disabling wait state on Chip Select 0
                str     r1, [r0]

;------------------------------------------------------------------------------
;- low level init
;----------------
; Call __low_level_init to perform initialization before initializing
; AIC and calling main.
;----------------------------------------------------------------------
;.import __low_level_init
;               bl      __low_level_init

;------------------------------------------------------------------------------
;- Reset the Interrupt Controller
;--------------------------------
;- Normally, the code is executed only if a reset has been actually performed.
;- So, the AIC initialization resumes at setting up the default vectors.
;------------------------------------------------------------------------------
;- Load the AIC Base Address and the default handler addresses
                 add     r0, pc,AicData-8-.  ; @ where to read values (relative)

                 ldmia   r0, {r1-r4}

;- Setup the Spurious Vector
                 str     r4, [r1, #AIC_SPU]      ; r4 = spurious handler


;- ICE note : For ICE debug
;- Perform 8 End Of Interrupt Command to make sure AIC will not lock out nIRQ
                mov         r0, #8
LoopAic0:
                str         r1, [r1, #AIC_EOICR]    ; any value written