📄 lib_at91.s79
字号:
CFI EndBlock cfiBlock0
; 186
; 187 //* End
; 188 }
; 189 //*----------------------------------------------------------------------------
; 190 //* Function Name : at91_pio_close
; 191 //* Object : Cancel PIO Controller handling from pins managed by
; 192 //* a peripheral
; 193 //* Input Parameters : <pio_pt> = PIO Descriptor pointer
; 194 //* : <mask> = defines the pins to managed by peripheral
; 195 //* Output Parameters : none
; 196 //* Functions called : none
; 197 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock1 Using cfiCommon0
CFI Function at91_pio_close
CODE32
; 198 void at91_pio_close ( const PioCtrlDesc *pio_pt, u_int mask )
; 199 //* Begin
; 200 {
; 201 //* Define PIOs to be controlled by peripherals
; 202 pio_pt->pio_base->PIO_PDR = mask ;
at91_pio_close:
LDR R2,[R0, #+0]
STR R1,[R2, #+4]
; 203
; 204 //* End
; 205 }
MOV PC,LR ;; return
CFI EndBlock cfiBlock1
; 206
; 207 //*----------------------------------------------------------------------------
; 208 //* Function Name : at91_pio_write
; 209 //* Object : Write a data on required PIOs
; 210 //* Input Parameters : <pio_pt> = PIO Controller Descriptor Address
; 211 //* : <mask> = defines work pins
; 212 //* : <state> = defines set ( =0) or clear ( #0)
; 213 //* Output Parameters : none
; 214 //* Functions called : none
; 215 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock2 Using cfiCommon0
CFI Function at91_pio_write
CODE32
; 216 void at91_pio_write ( const PioCtrlDesc *pio_pt, u_int mask, u_int state )
; 217 //* Begin
; 218 {
; 219 if (state == PIO_CLEAR_OUT )
at91_pio_write:
CMP R2,#+0x1
LDR R2,[R0, #+0]
; 220 {
; 221 //* Clear PIOs with data at 0 in CODR (Clear Output Data Register)
; 222 pio_pt->pio_base->PIO_CODR = mask ;
STREQ R1,[R2, #+52]
; 223 }
; 224 else
; 225 {
; 226 //* Set PIOs with data at 1 in SODR (Set Output Data Register)
; 227 pio_pt->pio_base->PIO_SODR = mask ;
; 228 }
; 229
; 230 //* End
; 231 }
MOVEQ PC,LR ;; return
STR R1,[R2, #+48]
MOV PC,LR ;; return
CFI EndBlock cfiBlock2
; 232 //*----------------------------------------------------------------------------
; 233 //* Function Name : at91_pio_read
; 234 //* Object : Read the state of the PIO pins
; 235 //* Input Parameters : <pio_pt> = PIO Controller Descriptor Address
; 236 //* Output Parameters : defines the pins value
; 237 //* Functions called : at91_clock_get_status, at91_clock_open,
; 238 //* at91_clock_close
; 239 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock3 Using cfiCommon0
CFI Function at91_pio_read
CODE32
; 240 u_int at91_pio_read ( const PioCtrlDesc *pio_pt)
; 241
; 242 //* Begin
; 243 {
at91_pio_read:
STMDB SP!,{R4-R7,LR} ;; Push
CFI RET Frame(CFA, -4)
CFI R7 Frame(CFA, -8)
CFI R6 Frame(CFA, -12)
CFI R5 Frame(CFA, -16)
CFI R4 Frame(CFA, -20)
CFI CFA SP+20
MOV R4,R0
; 244
; 245 u_int return_val ;
; 246 u_int save_clock ;
; 247
; 248 //* Get clock Status
; 249 save_clock = at91_clock_get_status ( pio_pt->periph_id ) ;
MOV R5,R4
LDRB R0,[R5, #+4]
MVN R1,#+0xF3
SUB R1,R1,#+0xBF00
LDR R2,[R1, #+0]
MOV R1,#+0x1
AND R7,R2,R1, LSL R0
; 250
; 251 //* Enable the PIO Clock
; 252 at91_clock_open ( pio_pt->periph_id ) ;
BL at91_clock_open
; 253
; 254 //* Read the Data in input of the PIO Controller
; 255 return_val = pio_pt->pio_base->PIO_PDSR ;
LDR R0,[R5, #+0]
LDR R6,[R0, #+60]
; 256
; 257 //* If PIO controller clock was disabled
; 258 if (( save_clock & (1 << pio_pt->periph_id)) == 0 )
LDRB R0,[R5, #+4]
MOV R1,#+0x1
AND R1,R7,R1, LSL R0
CMP R1,#+0x0
; 259 {
; 260 //* Disable the PIO Clock
; 261 at91_clock_close ( pio_pt->periph_id ) ;
BLEQ at91_clock_close
; 262 }
; 263
; 264 return (return_val);
MOV R0,R6
LDMIA SP!,{R4-R7,PC} ;; return
CFI EndBlock cfiBlock3
; 265
; 266 //* End
; 267 }
; 268
; 269 //*----------------------------------------------------------------------------
; 270 //* Function Name : at91_pio_set_mode
; 271 //* Object : Modify the mode of PIOs
; 272 //* Input Parameters : <pio_pt> = PIO Controller Descriptor
; 273 //* : <mask> = bit mask identifying the PIOs
; 274 //* : <mode> = the required PIOs configuration
; 275 //* Output Parameters : none
; 276 //* Functions called : none
; 277 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock4 Using cfiCommon0
CFI Function at91_pio_set_mode
CODE32
; 278 void at91_pio_set_mode ( const PioCtrlDesc *pio_pt, u_int mask, u_int mode )
; 279 //* Begin
; 280 {
; 281 //* If PIOs required to be filtered
; 282 if ((mode & PIO_FILTER_BIT) != 0 )
at91_pio_set_mode:
AND R3,R2,#+0xFF ;; Zero extend
TST R3,#+0x2
LDR R3,[R0, #+0]
; 283 //* Enable the filter on PIOs
; 284 pio_pt->pio_base->PIO_IFER = mask ;
STRNE R1,[R3, #+32]
; 285 //* Else
; 286 else
; 287 //* Disable the filter on PIOs
; 288 pio_pt->pio_base->PIO_IFDR = mask ;
STREQ R1,[R3, #+36]
; 289
; 290 //* If PIOs required to be open-drain
; 291 if ((mode & PIO_OPENDRAIN_BIT) != 0 )
AND R2,R2,#+0xFF ;; Zero extend
TST R2,#+0x4
LDR R2,[R0, #+0]
; 292 //* Enable the filter on PIOs
; 293 pio_pt->pio_base->PIO_MDER = mask ;
STRNE R1,[R2, #+80]
; 294 //* Else
; 295 else
; 296 //* Disable the filter on PIOs
; 297 pio_pt->pio_base->PIO_MDSR = mask ;
; 298 //* End
; 299 }
MOVNE PC,LR ;; return
STR R1,[R2, #+88]
MOV PC,LR ;; return
CFI EndBlock cfiBlock4
; 300 //*----------------------------------------------------------------------------
; 301 //* Function Name : at91_clock_set_mode
; 302 //* Object : Set System Clock Mode.
; 303 //* Input Parameters : <mode> = mode to define
; 304 //* Output Parameters : none
; 305 //* Functions called : at91_error
; 306 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock5 Using cfiCommon0
CFI Function at91_clock_set_mode
CODE32
; 307 void at91_clock_set_mode ( u_int mode )
; 308 //* Begin
; 309 {
at91_clock_set_mode:
STMDB SP!,{LR} ;; Push
CFI RET Frame(CFA, -4)
CFI CFA SP+4
; 310 //* Depending on the required mode
; 311 switch (mode)
CMP R0,#+0x1
BEQ ??at91_clock_set_mode_0
CMP R0,#+0x2
BEQ ??at91_clock_set_mode_1
CMP R0,#+0x3
BEQ ??at91_clock_set_mode_2
; 312 {
; 313 //* Idle mode required
; 314 case PS_MODE_IDLE:
; 315 //* Write the System Clock Disable Register
; 316 PS_BASE->PS_CR = PS_ARM7DIS ;
; 317 break ;
; 318
; 319 //* Active all peripheral clocks
; 320 case PS_ALL_PERIPH_ACTIVE:
; 321 //* Enable all the peripheral clocks
; 322 PS_BASE->PS_PCER = 0xFFFFFFFF ;
; 323 break ;
; 324
; 325 //* Desactive all peripheral clocks
; 326 case PS_ALL_PERIPH_INACTIVE:
; 327 //* Disable all the peripheral clocks
; 328 PS_BASE->PS_PCDR = 0xFFFFFFFF ;
; 329 break ;
; 330
; 331 //* EndSwitch
; 332 }
; 333 }
LDMIA SP!,{PC} ;; return
??at91_clock_set_mode_0:
MOV R0,#+0x1
MVN R1,#+0xFF
B ??at91_clock_set_mode_3
??at91_clock_set_mode_1:
MVN R0,#+0x0
MVN R1,#+0xFB
B ??at91_clock_set_mode_3
??at91_clock_set_mode_2:
MVN R0,#+0x0
MVN R1,#+0xF7
??at91_clock_set_mode_3:
SUB R1,R1,#+0xBF00
STR R0,[R1, #+0]
LDMIA SP!,{PC} ;; return
CFI EndBlock cfiBlock5
; 334 //* End
; 335
; 336 //*----------------------------------------------------------------------------
; 337 //* Function Name : at91_clock_open
; 338 //* Object : Enable the peripheral clock
; 339 //* Input Parameters : <periph_id> = peripheral identifier
; 340 //* Output Parameters : none
; 341 //* Functions called : none
; 342 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock6 Using cfiCommon0
CFI Function at91_clock_open
CODE32
; 343 void at91_clock_open ( u_int periph_id )
; 344 //* Begin
; 345 {
; 346 //* Write the Peripheral Clock Enable Register
; 347 PS_BASE->PS_PCER = (1<<periph_id) ;
at91_clock_open:
MOV R1,#+0x1
AND R0,R0,#+0xFF ;; Zero extend
MOV R0,R1, LSL R0
MVN R1,#+0xFB
B ??Subroutine1_0
CFI EndBlock cfiBlock6
; 348 //* End
; 349 }
; 350
; 351 //*----------------------------------------------------------------------------
; 352 //* Function Name : at91_clock_close
; 353 //* Object : Disable the clock of a Peripheral
; 354 //* Input Parameters : <periph_id> = peripheral identifier
; 355 //* Output Parameters : none
; 356 //* Functions called : none
; 357 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock7 Using cfiCommon0
CFI Function at91_clock_close
CODE32
; 358 void at91_clock_close ( u_int periph_id )
at91_clock_close:
REQUIRE ??Subroutine1_0
; 359 //* Begin
; 360 {
; 361 //* Write the Peripheral Clock Disable Register
; 362 PS_BASE->PS_PCDR = (1<<periph_id) ;
MOV R1,#+0x1
AND R0,R0,#+0xFF ;; Zero extend
MOV R0,R1, LSL R0
MVN R1,#+0xF7
CFI EndBlock cfiBlock7
; 363 //* End
; 364 }
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock8 Using cfiCommon0
CFI NoFunction
??Subroutine1_0:
SUB R1,R1,#+0xBF00
??Subroutine1_1:
STR R0,[R1, #+0]
MOV PC,LR ;; return
CFI EndBlock cfiBlock8
; 365
; 366 //*----------------------------------------------------------------------------
; 367 //* Function Name : at91_clock_get_status
; 368 //* Object : Return the Peripheral clock status
; 369 //* Input Parameters : <periph_id> = peripheral identifier
; 370 //* Output Parameters : none
; 371 //* Functions called : none
; 372 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock9 Using cfiCommon0
CFI Function at91_clock_get_status
CODE32
; 373 u_int at91_clock_get_status ( u_int periph_id )
; 374 //* Begin
; 375 {
; 376 //* Return the Peripheral Clock Status Register
; 377 return ( PS_BASE->PS_PCSR & (1<<periph_id) ) ;
at91_clock_get_status:
MVN R1,#+0xF3
SUB R1,R1,#+0xBF00
LDR R2,[R1, #+0]
MOV R1,#+0x1
AND R0,R0,#+0xFF ;; Zero extend
AND R0,R2,R1, LSL R0
MOV PC,LR ;; return
CFI EndBlock cfiBlock9
; 378 //* End
; 379 }
; 380
; 381 //*----------------------------------------------------------------------------
; 382 //* Function Name : at91_usart_open
; 383 //* Object : Initialize an USART.
; 384 //* Input Parameters : <usart_pt> = the USART to initialize
; 385 //* : <mode> = the Mode Register to be programmed
; 386 //* : <speed> = the BRDR to be programmed
; 387 //* : <timeguard> = the US_TTGR to be programmed
; 388 //* Output Parameters : None
; 389 //* Functions called : at91_clock_open, at91_pio_close
; 390 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Block cfiBlock10 Using cfiCommon0
CFI Function at91_usart_open
CODE32
; 391 void at91_usart_open ( const UsartDesc *usart_pt ,
; 392 u_int mode ,
; 393 u_int speed ,
; 394 u_int timeguard )
; 395 //* Begin
; 396 {
at91_usart_open:
STMDB SP!,{R4-R8,LR} ;; Push
CFI RET Frame(CFA, -4)
CFI R8 Frame(CFA, -8)
CFI R7 Frame(CFA, -12)
CFI R6 Frame(CFA, -16)
CFI R5 Frame(CFA, -20)
CFI R4 Frame(CFA, -24)
CFI CFA SP+24
MOV R4,R0
MOV R5,R1
MOV R6,R2
MOV R7,R3
; 397 //* Enable the clock
; 398 at91_clock_open ( usart_pt->periph_id ) ;
MOV R8,R4
LDRB R0,[R8, #+11]
BL at91_clock_open
; 399
; 400 //* If External clock used
; 401 if (( mode & SCK_USED ) != 0 )
MOV R0,#+0x20
ADD R0,R0,#+0x40000
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -